1. 林永隆 (Youn-Long Lin) Department of Computer Science National Tsing Hua University High-Level Synthesis of VLSIs THEDA Tsing Hua Electronic Design Automation

2. 2 VLSI Design Tools Design Capturing/Entry Analysis and Characterization Synthesis/Optimization –Physical (Floor planning, Placement, Routing) –Logic (FSM, Retiming, Sizing, DFT) –High Level(RTL, Behavioral) Management

3. 3 Design Methodology Progress Capture and Simulate Describe and SynthesisSpecify and ???

4. 4 Productivity Re-Targetability Correctness Why Synthesis? Unsynthesizability Performance Loss Inertial Why not Synthesis?

5. 5 StructuralBehavioral Physical X’tor Gate RTL Block Boolean FSM Algorithm GDSII Placement Floorplan Y-Chart Dan D Gajski

6. 6 StructuralBehavioral Physical X’tor Gate RTL Block Boolean FSM Algorithm GDSII Placement Floorplan Layout Synthesis

7. 7 StructuralBehavioral Physical X’tor Gate RTL Block Boolean FSM Algorithm GDSII Placement Floorplan Logic Synthesis

8. 8 StructuralBehavioral Physical X’tor Gate RTL Block Boolean FSM Algorithm GDSII Placement Floorplan High-Level Synthesis

9. 9 High Level Synthesis CDFG Parsing Transformation Synthesis Structural RTL Behavioral Description

10. 10 What Went Wrong? Too much emphasis on incremental work on algorithms and point tools Unrealistic assumption on component capability, architectures, timing, etc Lack of quality-measurement from the low level Too much promising on fully automation (silicon compiler??)

11. 11 Essential Issues Behavioral Specification Languages Target Architectures Intermediate Representation Operation Scheduling Allocation/Binding Control Generation

12. 12 Behavioral Specification Languages Add hardware-specific constructs to existing languages –HardwareC Popular HDL –Verilog, VHDL Synthesis-oriented HDL –UDL/I

13. 13 Target Architectures Bus-based Multiplexer-based Register file Pipelined RISC, VLIW Interface Protocol

14. 14 Design Space Exploration Arch I Arch II Arch III Delay Area

15. 15 FSM with Data Path (FSMD) FSM Data Path FSM Data Path FSM Data Path Interactive FSMDs

16. 16 Intermediate Representation ** + Control Flow Graph Data Flow Graph

17. 17 Scheduling (Temporal Binding) Time & Resource Tradeoff Time-Constrained –Integer Linear Programming (ILP) –Force-Directed Resource-Constrained –List Scheduling Other Heuristics –Simulated Annealing, Tabu Search,...

18. 18 Allocation/Binding Functional Units Operations Storage Variables Signals Bus/Wire/Mux Data Transfers

19. 19 RF FU RF Variables/Signals Data Transfer Operations

20. 20 Controller Specification Generation Scheduled CDFG Allocated Datapath Micro-Operations for Every Control Step

21. 21 HLS Quality Measures Performance Area Cost Power Consumption Testability Reusability

22. 22 Hardware Variations Functional Units –Pipelined, Multi-Cycle, Chained, Multi- Function Storage –Register, RF, Multi-Ported, RAM, ROM, FIFO, Distributed Interconnect –Bus, Segmented Bus, Mux, Protocol-Based

23. 23 Functional Unit Variations + * * * * - + Step 1 Step 2 Step 3 Step 4 + + +

24. 24 Storage/Interconnect Variations RF FU RF Segmented Buses Distributed FIFO Mux Chaining Multi-Port

25. 25 Architectural Pipelining FSM Data Path

26. 26 THEDA’s Work on HLS ILP-based Scheduling Bipartite Weighted Matching for Datapath Allocation Performance-Driven Interconnect Synthesis Loop Folding & Retiming Integrating Synthesis and Layout DSP Core Generation Book on HLS

27. 27 Integer Linear Programming for Scheduling Given # Control Steps ASAP + ALAP ==> Possible Steps for each Operations Tight Constraints on –Dependency –One Scheduled Step per Op –Resource Usage per Step Many Extensions

28. 28 Advanced Scheduling for Loop Folding 1 2 3 3 2 1 1 iteration per 3 cycles1 iteration per 2 cycles

29. 29 Loop Folding(cont.) 1 2 3 PrologueEpilogue Folded Body

30. 30 Retiming and Loop Folding 1 2 3 BACDEFBACDEF 1 2 3 BA CD E FB AC D E F

31. 31 Integrating Layout and Synthesis HDL Description HDL Synthesis RC Extraction & Delay Calculation Chip Layout Post-Layout Timing Analysis Module Resynthesis Timing Ok & no more area improvement P&R Soft-Macro Placement Block Placement Soft-Macro Formation No Module Resynthesis Soft-Macro Placement Soft-Macro Formation

32. 32 HLS Techniques for DSP Code Generation Memory Allocation SchedulingAddress Generation

33. 33 Applications of HLS Technology Code generation for embedded processors Retargetable compilers for application- specific instruction-set processors (ASIP) Reconfigurable computing Advanced features in logic synthesizer

34. 34 System-on-a-Chip ProcessorMemory External Memory Interface IPBus MasterUART Wireless Bridge USB

35. 35 SOC with PLDs ProcessorMemory External Memory Interface FPGABus MasterFPGA Wireless Bridge USB

36. 36 Wafer Foundry System Houses/ IC Vendors (Fabless) Integrators Library/ IP Vendors (Chipless) EDA Vendors Paradigm Shift

37. 37 IP and Synthesis Authoring IP for Synthesis Synthesis utilizing IP Synthesizing IPs Executable Data Sheets

38. 38 Executable Data Sheets IP IP Wrapper More than just the Port Interface

39. 39 Future Directions Realistic Methodology –Evolutional Transition from Current Practice –Domain Specific IP-Centric –As both Authoring Aid and Integrator Software –Co-design and Code Generation

40. 40 Value Time EDA IP IC