1. Symbolic Reduction of Quantum Circuits

2. Motivation In classical computation, it is desirable to find a “minimal” circuit to compute a given function In classical computation, it is desirable to find a “minimal” circuit to compute a given function In quantum computation this problem becomes essential, as longer circuits will necessarily be harder to insulate from decoherence. In quantum computation this problem becomes essential, as longer circuits will necessarily be harder to insulate from decoherence.

3. Background Any quantum operator can be “simulated” using the controlled-not gate and (arbitrary) one qubit rotations. Any quantum operator can be “simulated” using the controlled-not gate and (arbitrary) one qubit rotations. An arbitrary one qubit rotation can be written as S(w)T(x)R(y)T(z), where R, S, T are elementary gate families parameterized by angle. An arbitrary one qubit rotation can be written as S(w)T(x)R(y)T(z), where R, S, T are elementary gate families parameterized by angle. Furthermore, in a paper by Cybenko, an explicit decomposition of an arbitrary quantum operator into R, S, T and CNOT gates is given. Furthermore, in a paper by Cybenko, an explicit decomposition of an arbitrary quantum operator into R, S, T and CNOT gates is given.

4. Symbolic Reduction The basic idea: take a circuit and a set of reduction rules – that is, transformations that preserve the operation performed by the circuit while decreasing the total number of gates – search the circuit for places to apply these. The basic idea: take a circuit and a set of reduction rules – that is, transformations that preserve the operation performed by the circuit while decreasing the total number of gates – search the circuit for places to apply these. Note that this is necessarily an iterative process; one reduction may allow another which was previously impossible. Note that this is necessarily an iterative process; one reduction may allow another which was previously impossible.

5. Some Reduction Rules It happens that R(0), S(0), and T(0) are all the identity. These gates, if seen, may be removed. It happens that R(0), S(0), and T(0) are all the identity. These gates, if seen, may be removed. If two NOT (or CNOT) gates occur “next to” each other, remove them both. If two NOT (or CNOT) gates occur “next to” each other, remove them both. For X in {R,S,T}, if an X(a) is “next to” X(b), combine X(a) and X(b) into X(a + b). For X in {R,S,T}, if an X(a) is “next to” X(b), combine X(a) and X(b) into X(a + b).

8. Obstacles to Reduction For specific circuits, it is evident that the biggest obstacles to reduction are long chains of CNOT gates. For specific circuits, it is evident that the biggest obstacles to reduction are long chains of CNOT gates.