1. JTAG testing with XJTAG

2. XJTAG – Not what you have thought of…

3. The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen PeledContents Main Concepts Main Concepts System Components System Components XJTAG Software XJTAG Software Summary – Special Features Summary – Special Features

4. The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled Main Concepts Device centric philosophy Device centric philosophy Reactive test pattern generation Reactive test pattern generation

5. The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled The device-centric philosophy Tests are written from the perspective of the device being tested, without reference to the circuit. Tests are written from the perspective of the device being tested, without reference to the circuit. A set of tests written for a device can be used at any time, in any circuit. A set of tests written for a device can be used at any time, in any circuit. XJTAG is supplied with a set of ‘ device files ’, containing tests, so it is possible to create a test system without having to write any test code at all. XJTAG is supplied with a set of ‘ device files ’, containing tests, so it is possible to create a test system without having to write any test code at all. Any work done in creating tests at an early stage will not be lost, but can easily be modified to form part of a more fully-featured test system later. Any work done in creating tests at an early stage will not be lost, but can easily be modified to form part of a more fully-featured test system later.

6. The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled Reactive test pattern generation Using the current state of the board to determine the test patterns that should be generated. Using the current state of the board to determine the test patterns that should be generated.

7. The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen PeledSystem Components

8. The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled System Components Unit Under Test XJTAG Project File XJEngine XJLink XJEase Device Files XJInter- connect USB to JTAG adapter High speed – 480 Mbps Power supply to low-power target systems Test-Patterns generator Identifies manufacturing faults The information required to create a test pattern The testing of non-JTAG devices

9. The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled XJLink

10. The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled XJLink Connecting the test system to the circuit high-speed JTAG access from any computer with a USB interface. high-speed JTAG access from any computer with a USB interface. ability to configure the pin mapping between the XJLink and the circuit under test. ability to configure the pin mapping between the XJLink and the circuit under test. Standard pin mappings can be selected: Standard pin mappings can be selected: Multiice  Multiice  Xilinx  Xilinx  Altera Byte Blaster  Altera Byte Blaster  alternatively, the pin mapping can be set up to match other specific, non-standard, layouts. alternatively, the pin mapping can be set up to match other specific, non-standard, layouts.

11. The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled XJEngine

12. The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled High-level, C-like test description language of XJTAG. High-level, C-like test description language of XJTAG. Used for creating the tests. Used for creating the tests. Used for programing: Used for programing: JTAG devices (CPLDs, FPGAs) JTAG devices (CPLDs, FPGAs) Non-JTAG devices (FLASH) Non-JTAG devices (FLASH) Built-in interconnect test. Built-in interconnect test. XJEngine

13. The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen PeledXJEngine Generating the test patterns that implement the device tests. Generating the test patterns that implement the device tests. What a test pattern has to achieve in terms of setting pin values is controlled by the device file. What a test pattern has to achieve in terms of setting pin values is controlled by the device file. The information required to create a test pattern to fulfil that requirement comes from the project file. The information required to create a test pattern to fulfil that requirement comes from the project file. All of these test patterns are generated as the test system is running. This means that the XJEngine is able to feed the current status of devices in the circuit back to the controlling XJEase device test. This information is used to programmatically control the next test pattern that the XJEngine must generate. All of these test patterns are generated as the test system is running. This means that the XJEngine is able to feed the current status of devices in the circuit back to the controlling XJEase device test. This information is used to programmatically control the next test pattern that the XJEngine must generate.

14. The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled a device needs to be put into a particular mode to enable testing. a device needs to be put into a particular mode to enable testing. XJEase device test simply describes the pins that need to be driven for the device to enter the testable mode; XJEase device test simply describes the pins that need to be driven for the device to enter the testable mode; The test then loops, reading the device state, until a value is read that indicates that the mode has been entered The test then loops, reading the device state, until a value is read that indicates that the mode has been entered The test can proceed The test can proceed XJEngine (cont.) Consider the following case: Tests for such a device are only made possible by XJTAG’s circuit interaction.

15. The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled XJInter- connect

16. The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled XJInterconnect Manufacturing validation Identifies manufacturing faults: Identifies manufacturing faults: short circuits short circuits open circuits open circuits Stuck-at faults Stuck-at faults proprietary connection test algorithm proprietary connection test algorithm high percentage of circuit coverage high percentage of circuit coverage fault reporting that identifies the exact nature and location of faults fault reporting that identifies the exact nature and location of faults

17. The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled Example of a situation that causes a major problem for many JTAG connection tests A simple short circuit, such as that shown between nets C and D, can be identified A simple short circuit, such as that shown between nets C and D, can be identified HOWEVER, the inline resistors in nets A and B mean that the short circuit between those two nets would not be detected HOWEVER, the inline resistors in nets A and B mean that the short circuit between those two nets would not be detected The XJInterconnect connection test algorithm overcomes this problem. The XJInterconnect connection test algorithm overcomes this problem. When a test inconsistency is identified, more tests are automatically generated to pinpoint the nature and location of that fault. When a test inconsistency is identified, more tests are automatically generated to pinpoint the nature and location of that fault.

18. The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled XJEase Device Files

19. The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled XJEase Device Files Functional testing of non-JTAG devices The testing of non-JTAG devices is controlled by the 'XJEase device files'. The testing of non-JTAG devices is controlled by the 'XJEase device files'. Contain high-level test descriptions for each device being tested. Contain high-level test descriptions for each device being tested. Do not contain any information relating to how those tests should be implemented in the particular circuit under test Do not contain any information relating to how those tests should be implemented in the particular circuit under test Thus all tests developed are re-usable both within and across projects Thus all tests developed are re-usable both within and across projects

20. The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen PeledXJTAG Software

21. The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled A powerful graphical tool for: A powerful graphical tool for: JTAG chain visualization JTAG chain visualization fast chain validation fast chain validation circuit debug. circuit debug. Checks the integrity of the JTAG chain by extracting the ID code from each device in that chain. Checks the integrity of the JTAG chain by extracting the ID code from each device in that chain. uses the ID codes extracted to identify the appropriate BSDL files from its library. uses the ID codes extracted to identify the appropriate BSDL files from its library. XJAnalyser JTAG chain validation

22. The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled The main chain window in XJAnalyser A JTAG chain consisting of three devices: A JTAG chain consisting of three devices: Two are normally packaged Two are normally packaged The third is a BGA device The third is a BGA device The colours of the pins indicate their current values. The colours of the pins indicate their current values. XJAnalyser can set the values for output and bi-directional pins to high, low, fast oscillating and slow oscillating XJAnalyser can set the values for output and bi-directional pins to high, low, fast oscillating and slow oscillating XJAnalyser can also display information about the pins in a circuit on a per-device basis or about a selection of pins. XJAnalyser can also display information about the pins in a circuit on a per-device basis or about a selection of pins. This enables direct access to specific information of interest This enables direct access to specific information of interest XJAnalyser - Example information about the pins in a circuit on a per-device basis information about the a selection of pins

23. The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen PeledXJRunner A run-only environment for XJEase tests. A run-only environment for XJEase tests. Enabling tests to be run quickly and easily in a production environment. Enabling tests to be run quickly and easily in a production environment.

24. The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen PeledSummary – Special Features

25. The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled Summary - Special Features Pre Design Pre Design XJTAG ’ s design for test guidelines help to ensure that the eventual design of a circuit will yield the highest possible test coverage for all devices whether or not they comply with the JTAG standard. XJTAG ’ s design for test guidelines help to ensure that the eventual design of a circuit will yield the highest possible test coverage for all devices whether or not they comply with the JTAG standard. Design Validation Design Validation The process of testing can begin before the first circuit board has been produced The process of testing can begin before the first circuit board has been produced XJTAG can produce a design for test report with no hardware attached, to check that the circuit layout provides all of the connections required to implement the specified tests XJTAG can produce a design for test report with no hardware attached, to check that the circuit layout provides all of the connections required to implement the specified tests Circuit Testing Circuit Testing XJTAG testing can begin before the circuit (or even the whole JTAG chain) is fully populated XJTAG testing can begin before the circuit (or even the whole JTAG chain) is fully populated

26. The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled Multiple levels of abstraction Multiple levels of abstraction The core of XJTAG ’ s device centric philosophy The core of XJTAG ’ s device centric philosophy Test systems can be developed very quickly: Test systems can be developed very quickly: Tests are created by simply describing the pins that need to be set and the values that should result Tests are created by simply describing the pins that need to be set and the values that should result All tests that are developed can be reused whenever that device is used in other circuits All tests that are developed can be reused whenever that device is used in other circuits Any changes to a circuits netlist will require no reworking of the test system Any changes to a circuits netlist will require no reworking of the test system The test developer does not need to understand the intricacies of how JTAG works The test developer does not need to understand the intricacies of how JTAG works Summary - Special Features (cont.)

27. The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled Enhanced Flexibilty Enhanced Flexibilty There is no rigid order in which actions must occur There is no rigid order in which actions must occur Device programming can take place before testing starts, in the middle of the testing process and at the end Device programming can take place before testing starts, in the middle of the testing process and at the end XJTAG can implement the combination of testing and programming that yields the most effective result for each circuit XJTAG can implement the combination of testing and programming that yields the most effective result for each circuit Summary - Special Features (cont.)

28. The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled Summary - Special Features (cont.) One test system throughout the lifecycle of a circuit One test system throughout the lifecycle of a circuit Designers Designers Test engineers Test engineers Field engineers Field engineers

29. The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled XJTAG Clients

30. The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled Thank you for your attention