1. 30/05/06 T. Alt – KIP HeidelbergHLT-PRR : H-RORC H-RORC The HLT- Read-Out Receiver Card

2. 30/05/06 T. Alt – KIP HeidelbergHLT-PRR : H-RORC H-RORC v2.0

3. 30/05/06 T. Alt – KIP HeidelbergHLT-PRR : H-RORC Tasks Receiving of the raw detector data via optical links Injecting the data into the main memory of the hosts of the HLT front-end processors Sending processed data out of the HLT Pre-processing the data in the FPGA Reformatting and reordering of the data

4. 30/05/06 T. Alt – KIP HeidelbergHLT-PRR : H-RORC Functionality RORC Core –Xilinx Virtex4 LX40 FPGA –Xilinx Platform PROM for configuration –Xilinx LogiCORE PCI 66MHz/64bit –2 x half CMC interface to two DIU cards RORC X-tend –4 x DDR-SDRAM 166/200 MHz up to 1Gb/module –PCI-X 133/64 –2 x TagNET : fast serial full-duplex links –“secure remote configuration” with FLASH and CPLD –“Ready for Linux” (FAST-Ethernet, RS232, Flash memory)

5. 30/05/06 T. Alt – KIP HeidelbergHLT-PRR : H-RORC Core & X-tend XILINX VIRTEX4 LX40 DDR-SD TAGNET USER- FLASH CFG- FLASH PLATFORM PROM XC95144 CPLD CMC-Connector Power 1V2 Power 2V5 Power 1V8 TAGNET RS-232 ETH-PHY PCI-Power 3V3 MemoryConfiguration Serial links LVDS linksPOWER CMC-J11/J22 OSC PCI-66/64 - PCI-X 133/64

6. 30/05/06 T. Alt – KIP HeidelbergHLT-PRR : H-RORC Core only XILINX VIRTEX4 LX40 DDR-SD TAGNET USER- FLASH CFG- FLASH PLATFORM PROM XC95144 CPLD CMC-Connector Power 1V2 Power 2V5 Power 1V8 TAGNET RS-232 ETH-PHY PCI-66/64 - PCI-X 133/64 PCI-Power 3V3 MemoryConfiguration Serial links LVDS linksPOWER CMC-J11/J22 OSC

7. 30/05/06 T. Alt – KIP HeidelbergHLT-PRR : H-RORC TOP VIEW

8. 30/05/06 T. Alt – KIP HeidelbergHLT-PRR : H-RORC BOTTOM VIEW

9. 30/05/06 T. Alt – KIP HeidelbergHLT-PRR : H-RORC Verification The following tests have been successfully performed : - JTAG - PCI-33/32, PCI-33/64, PCI-66/32, PCI-66/64 - CMC-Connectors with DIU/SIU cards - Xilinx Platform PROM for configuration - Configuration with Flash & CPLD - DDR-SDRAM - TagNET The H-RORC passed CERNs Production Readiness Review in October 2005.

10. 30/05/06 T. Alt – KIP HeidelbergHLT-PRR : H-RORC PCI DMA Write Performance Measured performance of DMA data cycles on the PCI bus. Theoretical bandwidth of a 64bit/66MHz PCI bus: 528 MByte/s For each DMA block length 10/100/1000/10000 transactions have been performed. The time for each transaction was measured by a counter with a 15ns granularity. The transmitted data was checked for errors: No errors occurred max. 2xDIU data rate

11. 30/05/06 T. Alt – KIP HeidelbergHLT-PRR : H-RORC Summary & Sources The H-RORC is currently in production. A preproduction batch of 15 boards was received and is currently under testing. Schematics, Assembly and Bill of Materials can be found here http://www.kip.uni-heidelberg.de/wiki/HLT/ H-RORC PRR related changes : 2 panel leds JTAG chain connected to PCI large capacitors removed from the backside to achieve PCI compliance power consumption needs to be observed for each design but was no problem up to now documentation is on the web