1. 1 IRAM Testing / Verification Sam Williams UC Berkeley samw@cs.berkeley.edu

2. 2 Testing Intro Testing will be performed on each level of the design from ISA simulator through a VERILOG netlist, and also on actual parts. Level of testing will vary depending on capabilities. For functionality, tests are just snippets of assembly code in a specific test file format.

3. 3 Pass/Fail Determination Self-checking: provide register/memory true values to compare output of simulator against. Trace Comparison: each simulator produces an architectural trace (instruction, PC, registers modified, new values, memory addresses/values). Then compare any two simulators Directed: require user inspection, e.g. cache replacement policy

4. 4 Test File Format Simple text file divided into multiple sections (code, initialization, self-checking, simulator specific controls, variables, memory image) Random variables/sets can be used to produce very simple random self-checking tests Simulator controls allow configuration of simulators for a specific test Init/self-checking sections can set any register in any register file Wrapper incorporates all and creates the file(s) best suited for the simulators in question

5. 5 Wrapper (verify script) Parse, random test generation Temp files args Source file(s) Simulators Output files Comparator pass/fail unique failing random tests

6. 6 Comparator Gives pass/fail condition Compare traces generated from simulators. Looks for data miscompares, missing instructions, wrong destinations, etc… Currently only works on instruction level, not virtual processor. Can be used to generate/compare memory images from traces.

7. 7 Random Test Generator Single configuration file used to determine number of instructions, probability distributions, exceptions allowed, control structures, speculative, etc… Control structures: e.g. for-loop, if-else, jsr primitives Can insert code to prevent exceptions from occurring, e.g. prevent misaligned accesses Insert vsync’s to ensure vector-scalar memory coherency Complex primitives, e.g. dot products, matrix operations, etc… Can be used to create random regressions where paramaters are automatically varied

8. 8 Testing on Different Simulators ISA and performance simulator can take advantage of all methods For VERILOG and VERILOG netlist it is more difficult to implement a trace generator For silicon, it is essentially impossible to generate traces, and will not be possible to capture or even drive all pins. Solution is test through the JTAG interface. Requires the wrapper to run code to drive this interface with instructions, and extract results.

9. 9 Future Work Further develop “unique fail” determination code in verify script Fully implement trace generator for VERILOG simulator. (Allows more than simple self-checking tests and memory image generation) Implement code to drive JTAG interface to perform silicon testing. Support for testing external / asynchronous events Write many more self-checking and directed tests