1. Multiplexers, Decoders, and Programmable Logic Devices
Unit 9
Multiplexers, Decoders, and Programmable Logic Devices

2. Outlines 9.1 Introduction 9.2 Multiplexers 9.3 Three-State Buffers
9.4 Decoders and Encoders
9.5 Read-Only Memories
9.6 Programmable Logic Devices (PLD)
Programmable Logic Arrays (PLA)
Programmable Array Logic (PAL)
9.7 Complex Programmable Logic Devices (CPLD)
9.8 Field Programmable Gate Arrays (FPGA) ,,
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3. Integrated Circuits (1/2)
Integrated Circuits (IC) are classified by # of gates
Small-scale integration (SSI)
NAND, NOR, AND, OR, inverter, Flip-Flop
1-4 gates, 6 inverters, 1-2 Flip-flops
Medium-scale integration (MSI)
Adder, multiplexer, decoder, register, counter
gates
Large-scale integration (LSI)
Memories, microprocessors
100- a few thousand gates ,,
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4. Integrated Circuits (2/2)
Integrated Circuits (IC) are classified by # of gates
Very-large-scale integration (VLSI)
Microprocessors, FPGA, Application-specific integrated circuit (ASIC),…
Several thousand gates or more
Ultra Large-scale integration (ULSI)
Memories, microprocessors
More than 109 transistors
The cost of wiring, designing and maintaining of digital system is lower when LSI and VLSI functions are used. ,,
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5. Topics 9.1 Introduction 9.2 Multiplexers 9.3 Three-State Buffers
9.4 Decoders and Encoders
9.5 Read-Only Memories
9.6 Programmable Logic Devices (PLD)
Programmable Logic Arrays (PLA)
Programmable Array Logic (PAL)
9.7 Complex Programmable Logic Devices (CPLD)
9.8 Field Programmable Gate Arrays (FPGA) ,,
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6. Multiplexers (1/4) Multiplexers (MUX, or data selector)
A MUX has a group of data inputs and a group of control inputs.
The control inputs are used to select one of the data inputs and connect it to the output terminal.
2-to-1 MUX
A=0, Z=I0
A=1, Z=I1
Z=A’I0+AI1
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7. Multiplexers (2/4) 4-to-1, 8-to-1, 2n-to-1 MUX
Logic equation for 8-to-1 MUX
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8. Multiplexers (3/4)
Logic Diagram for 8-to-1 MUX
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9. Multiplexers (4/4) Logic equation for 2n-to-1 MUX
where is a minterm of the n control variables and is the corresponding data input
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10. DE-MUltipleXer (DEMUX)
DEMUX takes a single input and direct it to one of several outputs.
DEMUX
S0 S1 P0 P1 P2 P3 P0 P1 P2 P3
A A A A A
S0 S1
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11. Usage of Multiplexers (1/3)
Quad Multiplexer Used to Select Data
A=0, (z0z1z2z3)=(x0x1x2x3)
A=1, (z0z1z2z3)=(y0y1y2y3)
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12. Usage of Multiplexers (2/3)
Figure in page Block diagram for binary divider
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13. Usage of Multiplexers (3/3)
Use a 4-to-1 MUX to be an XOR gate
Use an 8-to-1 MUX to generate f(a,b,c)=Σm(1,3,4,7)
Use an 8-to-1 MUX to generate f(a,b,c,d)=Σm(0,1,3,6,7,8,11,12,14)
Multiplexed Transmission System
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14. Topics 9.1 Introduction 9.2 Multiplexers 9.3 Three-State Buffers
9.4 Decoders and Encoders
9.5 Read-Only Memories
9.6 Programmable Logic Devices (PLD)
Programmable Logic Arrays (PLA)
Programmable Array Logic (PAL)
9.7 Complex Programmable Logic Devices (CPLD)
9.8 Field Programmable Gate Arrays (FPGA) ,,
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15. Three-State Buffers (1/5)
A gate output can only be connected to a limited number of other device inputs without degrading the performance of a digital system.
A buffer may be used to increase the driving capability of a gate output.
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16. Three-State Buffers (2/5)
Three-state buffer (Tri-state buffer)
B=1, C=A. (C=0 or 1)
B=0, C=Z.
C acts like an open circuit.
C is effectively disconnected from the buffer output so that no current can flow.
This is referred to a Hi-Z (high-impedance) state of the output because the circuit offers a very high resistance or impedance to the flow of current.
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17. Three-State Buffers (3/5)
Four kinds of Three-State Buffers
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18. Three-State Buffers (4/5)
Data Selection Using Three-State Buffers
D=B’A+BC
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19. Three-State Buffers (5/5)
Circuit with Two Three-State Buffers
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20. Usage of Three-State Buffers (1/2)
4-Bit Adder with four sources for one operand
Use a 4-to-1 MUX to select one of several sources
Set up a three-state bus: A bus is driven by three-state buffers
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21. Usage of Three-State Buffers (2/2)
Bi-directional I/O Pin
Buffer is enabled, Output pin
Buffer is disabled, Input pin
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22. Topics 9.1 Introduction 9.2 Multiplexers 9.3 Three-State Buffers
9.4 Decoders and Encoders
9.5 Read-Only Memories
9.6 Programmable Logic Devices (PLD)
Programmable Logic Arrays (PLA)
Programmable Array Logic (PAL)
9.7 Complex Programmable Logic Devices (CPLD)
9.8 Field Programmable Gate Arrays (FPGA) ,,
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23. Decoders
To generates all of minterms: yi=mi
3-to-8 Decoder:
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24. 4-to-10 Line Decoder (1/2) 4-to-10 Line Decoder with Inverted Output
yi=mi’=Mi
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25. 4-to-10 Line Decoder (2/2)
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26. Usage of Line Decoder Realize the following functions using a decoder.
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27. Encoders The inverse function of a decoder 8-to-3 Priority Encoder
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28. Topics 9.1 Introduction 9.2 Multiplexers 9.3 Three-State Buffers
9.4 Decoders and Encoders
9.5 Read-Only Memories
9.6 Programmable Logic Devices (PLD)
Programmable Logic Arrays (PLA)
Programmable Array Logic (PAL)
9.7 Complex Programmable Logic Devices (CPLD)
9.8 Field Programmable Gate Arrays (FPGA) ,,
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29. Read-Only Memories (1/3)
Consists of semiconductor devices that interconnected to store binary data
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30. Read-Only Memories (2/3)
A ROM consists of a decoder and a memory array.
The basic architecture of ROM
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31. Read-Only Memories (3-1/3)
A=0 B=0 C=0
A=B=C=0: F=1010 A=B=C=1: F=0101 1 1
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32. Read-Only Memories (3-2/3)
A=1 B=1 C=1 1
A=B=C=0: F=1010 A=B=C=1: F=0101 1 1
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33. Usage of ROM (1/4)
A ROM can realize m functions (F1,F2,…Fn) of n variables.
Multiple-output combinational circuits can be realized using ROMs.
Realize the following functions using ROM.
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34. Usage of ROM (2/4)
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35. Usage of ROM (3/4)
Design a code converter that converts a 4-bit binary number to a hexadecimal digit and outputs the 7-bit ASCII code.
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36. Usage of ROM (4/4)
Because , the ROM needs only five outputs. The ROM size is 16 words by 5 bits. The decoder is a 4-to-16 decoder.
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37. Type of ROMs Mask-programmable ROMs Programmable ROMs (PROMs)
Electrically Erasable Programmable ROMs (EEPROMs, E2PROMs)
Flash memories
Flash memory has built-in programming and erase capability so that data can be written to it while it is in place in a circuit without the need for a separate programmer.
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38. Topics 9.1 Introduction 9.2 Multiplexers 9.3 Three-State Buffers
9.4 Decoders and Encoders
9.5 Read-Only Memories
9.6 Programmable Logic Devices (PLD)
Programmable Logic Arrays (PLA)
Programmable Array Logic (PAL)
9.7 Complex Programmable Logic Devices (CPLD)
9.8 Field Programmable Gate Arrays (FPGA) ,,
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39. Programmable Logic Devices
Programmable Logic Device (PLD) is a general name for a digital integrated circuit capable of being programmed to provide a variety of different logic functions.
Lower cost
Design a larger circuit
Changing the programming of PLD
Without having to change the wiring
Programmable logic arrays (PLAs)
Programmable array Logic devices (PALs)
Complex programmable logic devices (CPLDs)
Field-programmable gate arrays (FPGAs)
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40. PLA Perform the same basic function as a ROM
A PLA with n inputs and m outputs can realize k products of n variables then generate m functions .
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41. Example 1 of PLA (1/4) Realize the following functions using PLA.
Using a PLA with 4 inputs, 4 outputs and 5 internal product terms.
AND Array
Ex: A=1, B=0, C=1  m5=1  AC=1, others =0 F0=F1=F2=0, F3=1
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42. Example 1 of PLA (2/4)
Construct the PLA table.
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43. Example 1 of PLA (3/4)
AND-OR equivalent circuit
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44. Example 1 of PLA (4-14)
AND Array
OR Array
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45. Example 1 of PLA (4-2/4) 1 1 1 1 1
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46. Example 2 of PLA (1/2) Use PLA to realize f1,f2, and f3.
Using a PLA with 4 inputs, 3 outputs and 6 internal product terms.
Construct the PLA table
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47. Example 2 of PLA (2/2)
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48. PAL (1/2)
A special case of the PLA in which the AND array is programmable and the OR array is fixed.
Less expensive than the more general PLA
Easier to program
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49. PAL (2/2)
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50. Example of PAL
Implement a full adder using a PAL.
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51. Topics 9.1 Introduction 9.2 Multiplexers 9.3 Three-State Buffers
9.4 Decoders and Encoders
9.5 Read-Only Memories
9.6 Programmable Logic Devices (PLD)
Programmable Logic Arrays (PLA)
Programmable Array Logic (PAL)
9.7 Complex Programmable Logic Devices (CPLD)
9.8 Field Programmable Gate Arrays (FPGA) ,,
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52. CPLD (1/3)
Architecture of Xilinx XCR3064XL CPLD
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53. CPLD (2/3) 4 function blocks (FBs)
Each FB has 16 associated macrocells (MC1, MC2,…).
Each macrocell contains a flip-flop and multiplexers that route signals from the FB to the I/O block or to the interconnect array (IA)
Each FB is a programmable AND-OR array that is configured as a PLA.
The IA selects signals from the macrocell outputs or I/O blocks and connects them back to FB inputs.
A signal generated in one FB can be used as an input to any other FB.
The I/O blocks provide an interface between the bi-directional I/O pins on the IC and the interior of the CPLD.
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54. CPLD (3/3)
Data Flow in XCR3064XL CPLD
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55. Topics 9.1 Introduction 9.2 Multiplexers 9.3 Three-State Buffers
9.4 Decoders and Encoders
9.5 Read-Only Memories
9.6 Programmable Logic Devices (PLD)
Programmable Logic Arrays (PLA)
Programmable Array Logic (PAL)
9.7 Complex Programmable Logic Devices (CPLD)
9.8 Field Programmable Gate Arrays (FPGA) ,,
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56. FPGA
An FPGA is an IC that contains an array of identical logic cells with programmable interconnections.
The interior of the FPGA consists of an array of logic cells, called configurable logic blocks (CLBs).
The array of CLBs is surrounded by a ring of input-output interface blocks (I/O blocks).
The I/O blocks connect the CLB signals to IC pins.
The space between the CLBs is used to route connections between the CLB outputs and inputs.
The user can program the functions realized by each CLB and connections between CLBs.
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57. Layout of a Typical FPGA
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58. Configurable Logic Block (CLB)
A simplified CLB
2 Function generators ( implemented as lookup tables, LUTs)
2 Flip-flops (D-FFs)
5 MUXs for routing signals within CLB.
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59. Lookup Table (LUT) A reprogrammable ROM
Stores the truth table for a function
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60. Decomposition of Switching Functions
In order to implement a switching function of more than n variables using n-variable function generators (in FPGA), the function must be decomposed into subfunctions where each subfunctions requires only n variables or less.
Shannon’s Expansion Theorem
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61. Example 1 of Decomposition
Realization of Five-Variable Function with 4-input Function Generators
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62. Example 2 of Decomposition
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