1. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process

2. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process CMOS Process

3. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process CMOS Inverter Layout

4. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Patterning on Si

5. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Semiconductor fabrication (1) 2

6. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Semiconductor Fabrication (2) 1 4 3

7. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Semiconductor Fabrication (3) 3 3

8. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Semiconductor Fabrication (4) END 4

9. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Circuit Under Design This two-inverter circuit (of Figure 3.25 in the text) will be manufactured in a twin-well process.

10. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Circuit Layout Inverter 2Inverter 1 D1D1 D2D2 D4D4 S2S2 D3D3 S4S4 S1S1 S3S3 GND Vdd G1G1 G2G2G4G4 G3G3 pMOS-2 pMOS-1 nMOS-2 nMOS-1 IN1OUT2OUT1IN2 IN2=OUT1 B4 B2 B3 B1 Inverter 1 nMOS-1 pMOS-1 Inverter 2 nMOS-2 pMOS-2

11. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Start Material Starting wafer: n-type with doping level = 10 13 /cm 3 * Cross-sections will be shown along vertical line A-A’ Si n-type nMOS pMOS A A’A’ A A’A’

12. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process N-well Construction (1) Oxidize wafer (2) Deposit silicon nitride (3) Deposit photoresist Si n-type photoresist silicon nitride silicon dioxide nMOS pMOS

13. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process N-well Construction (4) Expose resist using n-well mask Si n type Exposed resist nMOS pMOS

14. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process N-well Construction (5) Develop resist (6) Etch nitride and (7) Grow thick oxide Si n type nMOS pMOS

15. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process N-well Construction (8) Implant n-dopants (phosphorus) (up to 1.5  m deep) thick oxide n-well Si n type nMOS pMOS

16. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process P-well Construction Repeat previous steps Si n type n-wellp-well pMOSnMOS pMOS

17. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Grow Gate Oxide Gate oxide 55 nm thin Si n type n-wellp-well pMOSnMOS pMOS

18. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Grow Thick Field Oxide Uses Active Area mask Is followed by threshold-adjusting implants Field Oxide 0.9  m thick Si n type n-wellp-well pMOSnMOS pMOS

19. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Polysilicon layer Polysilicon Deposition Si n type n-wellp-well pMOS nMOS pMOS

20. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Source-Drain Implants photoresist Si n type n-wellp-well pMOS nMOS pMOS

21. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Source-Drain Implants Si n type n-wellp-well pMOS nMOS GB S DBGSD pMOS

22. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Contact-Hole Definition (1) Deposit inter-level Dielectric (SiO 2 ) — 0.75  m (2) Define contact opening using contact mask Si n type n-wellp-well pMOS nMOS pMOS

23. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Aluminum-1 Layer Aluminum evaporated (0.8  m thick) followed by other metal layers and glass GB G S D B GSD IN OUT pMOS nMOS VddGND IN OUT nMOS pMOS

24. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Advanced Metalization

25. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Intel 0.09  m Generation

26. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Downsizing MOSFET below 0.1  m

27. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Design Rules

28. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Design Rules l Interface between designer and process engineer l Guidelines for constructing process masks l Unit dimension: Minimum line width »scalable design rules: lambda parameter »absolute dimensions (micron rules)

29. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process CMOS Process Layers Layer Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Well (p,n) Active Area (n+,p+) ColorRepresentation Yellow Green Red Blue Magenta Black Select (p+,n+) Green

30. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Intra-Layer Design Rules Metal2 4 3

31. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Transistor Layout Transistor

32. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Via’s and Contacts

33. Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process Select Layer