1. 31.05.04 הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל המעבדה למערכות ספרתיות מהירות High Speed Serial Link Traffic Generator & Analyzer Verification Midterm Presentation Midterm Presentation Author : Moshe Porian Supervisor : Boaz Mizrachi

2. Project Goals achieved Building a Generator Checker Unit for examination the Traffic Generator design. Building a Generator Checker Unit for examination the Traffic Generator design. Configure set of parameters and testing which demonstrate different phenomena of high speed serial links. Configure set of parameters and testing which demonstrate different phenomena of high speed serial links. Emulate the connection from the PC to the Generator design by building a PPC EMU Unit. Emulate the connection from the PC to the Generator design by building a PPC EMU Unit. Easy collect results by designing Compare Unit which report to log out file simple messages that direct the user to the bugs. Easy collect results by designing Compare Unit which report to log out file simple messages that direct the user to the bugs.

3. PPC EMU GENERATOR TGA Verification – Block Diagram Script File ANALYZER GENERATOR CHECKER Reference Model of the Analyzer Compare & Analyze Unit Log out File Config File RocketIO EMU Packet Generator For the Analyzer

4. PPC EMULATION  The Script syntax is as follows:  Read (, )  Write (,, )  Where :  = ‘P’ – Generator BRAM ‘T’ – Analyzer BRAM ‘T’ – Analyzer BRAM  = 32 bits: xxxxxxxxh

5. PPC EMU I/O Interface Every clock cycle the PPC EMU generate data & address outputs according to the instructions from script file. Every clock cycle the PPC EMU generate data & address outputs according to the instructions from script file.

6. PGP BRAM EMULATION

7. PGP BRAM EMU I/O Interface

8. PGP BRAM EMU functionality  The Generator address pattern is: x”ffff00##”  Every address is a multiple of 4 2^8)/4= 64  (2^8)/4= 64 Address space range of the PGP BRAM  Address space range of the PGP BRAM EMU is [0..63] EMU is [0..63]

9. Generator Checker Define registers and counters which survey the outputs of the GENERATOR Define registers and counters which survey the outputs of the GENERATOR verify that the results are appropriate to the instructions from the PPC EMULATION. verify that the results are appropriate to the instructions from the PPC EMULATION. Generator verification: Generator verification: Number of packets,Packet length,Header length, Stamp length,Burst size,Inter Burst Gap Inter Packet Gap,Header Data,Stamp Data, Start/End Padding Data

10. GEN CHECK I/O Interface

11. Packet Structure

12. GEN CHECK State Machine STAMP_DATAGAP_DATA END_TEST WAIT4SOP HEADER_DATA INIT_CONFG WAIT4POLLING INIT CNT LEN & ERR Ram data(0)='1' INIT CONFG REGS START='1' IDLE SOP ASSUME HEADER LEN CORRECT DATA = HEADER DATA = STAMP EOP IDLE SOP FINISH='1'

13. Compare and Analyze Unit  Compare between the Generator Checker results with the configurable parameters by the PPC EMU(from the script file) results with the configurable parameters by the PPC EMU(from the script file)  Analyze the results and report it to a log out file out file  The log out file includes simple messages that direct the user to the bugs that direct the user to the bugs

14. Write to a log out file the results

15. Open issues  8B/10B Encoding Bypassed  Reference Model of the Analyzer  Packet Generator for the Analyzer  Behavioral Simulation including integration of the Generator & Analyzer integration of the Generator & Analyzer

16. Schedule 9-30.3.04 - Project characterization 1-14.4.04 - Architecture/Spec Development 8-15.4.04 - Miluim… 18-21.4.04 - Architecture/Spec Development 22.4.04 - Project characterization Presentation 25.4-1.5.04 - Functional Architecture Approve 1.5-21.6.04 - VHDL Coding 10-17.5.04 - Project Design Presentation 21.6-15.7.04 - Behavior Simulation + VHDL Coding 15.7-30.7.04 - Project summarizing 27.7.04 - Project Presentation