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IDDQ Signatures1 New Graphical I DDQ Signatures Reduce Defect Level and Yield Loss (U. S. Patent Pending) New Graphical I DDQ Signatures Reduce Defect.

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Presentation on theme: "IDDQ Signatures1 New Graphical I DDQ Signatures Reduce Defect Level and Yield Loss (U. S. Patent Pending) New Graphical I DDQ Signatures Reduce Defect."— Presentation transcript:

1 IDDQ Signatures1 New Graphical I DDQ Signatures Reduce Defect Level and Yield Loss (U. S. Patent Pending) New Graphical I DDQ Signatures Reduce Defect Level and Yield Loss (U. S. Patent Pending) Lan Rao Michael L. Bushnell Vishwani Agrawal ECE Dept., Rutgers U., Piscataway, NJ

2 IDDQ Signatures2 IDDQ Testing VDD = 5V IDD Ground IDDQfault Ref. Chakravarty and Thadikaran, 1997

3 IDDQ Signatures3 IDDQ (microA) vs. Vector # A good chip A bad chip

4 IDDQ Signatures4 Two Proposed Approaches: New way #1 Use 135 IDDQ test vectors, instead of 10-20 vectors in real production line, collect all current measurements and plot current as function of test vector index. Use classifier software running on Automatic Test Equipment to classify chip as good or bad. Without using ‘stuck-at fault’ voltage test, but keeping the other voltage tests. New way #2 Only use graphical IDDQ testing method defined above. Potentially large cost saving for VLSI chip manufacturing test.

5 IDDQ Signatures5 Economics Analysis* Method Existing Current & Voltage Testing With New Graphical Current Testing Use Only Graphical Test # Measurements 8023(stuck-at)+53k (functional)+15232(delay) + 20(IDDQ) 135(IDDQ)+15232(delay)+53k(functional)135(IDDQ) Test time 14.55s 10.23 s 2.90s Production test cost 5 cents/s X 14.55s = 72.8cents 5 cents/s X 10.23s = 51.2cents 5 cents/sX2.9s= 14.5cents Cost savings 0%30.0%80.1% % Defective chips found 98.30% 99.85 % 96.1% Pattern gen. DifficultSimpler Much simpler DiagnosisComplexComplexComplex *With help from Dr. Phil Nigh, IBM.

6 IDDQ Signatures6 New Classification Features The shape of the entire curve of current measurements – # of bands that measurements cluster into. Width and separation of bands. Current glitch or smearing detection among all IDDQ measurements.

7 IDDQ Signatures7 IIDDQ Distribution Over Vectors is not Gaussian # of IDDQ values Good Devices Bad Devices IDDQ Only 156841592351 256742429546 34871144104 41236731 >41440

8 IDDQ Signatures8 Classification of DUT Good devices Devices passing all tests and all test steps. Devices passing all tests and all test steps. Devices that fail wafer probe test, but pass packaged test and burn-in, (poor wafer probe registration). Devices that fail wafer probe test, but pass packaged test and burn-in, (poor wafer probe registration). Bad devices Devices that failed the tests other than the IDDQ test. Devices that failed the tests other than the IDDQ test. Devices with extremely high IDDQ current. Devices with extremely high IDDQ current. IDDQ only Devices that failed on the IDDQ test with less than the absolute IDDQ threshold. Devices that failed on the IDDQ test with less than the absolute IDDQ threshold.

9 IDDQ Signatures9 Good vs. Faulty Chip (Single Band) Single band of a good chip Smeared (noisy) single band of a bad chip

10 IDDQ Signatures10 Good vs. Faulty Chip (Single Band with Spike) Good Chip Plot Faulty Chip with Noise Spikes

11 IDDQ Signatures11 Good vs. Faulty Chip (Multiple Bands) Good 2 Band Chip Faulty 2 Band Chip with Smearing

12 IDDQ Signatures12 Comparing IDDQ Test Methods Statistics (  A) Method Test Escape (8) Overkill (8) Test escape (25) Overkill (25) Test escape (450) Overkill (450) Single- threshold 6.4 % 1.6%6.8%2.2%7.5%2.3% Current difference 35.3 % 3%34%3%35%3.1%  IDDQ (4  A) 8.9 % 1.1%8.60.8%8.6%1.0%  IDDQ (ó =0.35) 7.3 % 6.6%7%6.7%7.6%6.8% Graphical IDDQ 5.0 % -2.8%5.4%-2.7%5.97% -2.5% Observation: The absolute threshold value is not critical for this technique.

13 IDDQ Signatures13 Test Method Efficiencies Test Method % Bad Chips Detected 8  A 450  A 52.6 % 61.5% 71.3 % 83.4% 70.3 % 82.2% 93.6 % 93.5% 96.1 % 96.1% 75.8% 88.6% IBM (functional+ stuck-at+delay) Statistics IBM Functional Test IBM Stuck-at Test IBM Delay Test IBM IDDQ Test Graphical IDDQ Test

14 IDDQ Signatures14 Test Vector Set Truncation Results # of IDDQ vectors Good devices out of 11,858 Bad devices out of 5,576 IDDQ only devices pass out of 1,032 # 1 (125) 11,7115,229167 # 1 + # 2 (135) 11,7155,240165 # 1 + # 3 (185) 11,7155,235154 # 1 + # 2 + # 3 (195) 11,7195,243153 50 random 11,6575,152222 100 random 11,7265,168176 140 random 11,7355,209172 Proper selection of test vector set can further improve the test quality.

15 IDDQ Signatures15 Conclusion Gaussian distribution of IDDQ measurements may not be true. We present a new way of IDDQ testing with lower test escape and lower yield loss (overkill rate). The new method does not rely on a single threshold or a single delta threshold, but on the shape of the measurement set, hence it is promising for deep submicron technology; can replace at least some voltage tests; the accuracy can be further improved by careful choice of the test vector set.

16 IDDQ Signatures16 Thank you!


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