1. EECC550 - Shaaban #1 Lec # 4 Winter 2000 12-13-2000 Major CPU Design Steps 1Using independent RTN, write the micro- operations required for all target ISA instructions. 2Construct the datapath required by the micro- operations identified in step 1. 3Identify and define the function of all control signals needed by the datapath. 3Control unit design, based on micro-operation timing and control signals identified: -Hard-Wired: Finite-state machine implementation. -Microprogrammed.

2. EECC550 - Shaaban #2 Lec # 4 Winter 2000 12-13-2000 Datapath Design Steps Write the micro-operation sequences required for a number of representative instructions using independent RTN. From the above, create an initial datapath by determining possible destinations for each data source (i.e registers, ALU). –This establishes the connectivity requirements (data paths, or connections) for datapath components. –Whenever multiple sources are connected to a single input, a multiplexer of appropriate size is added. Find the worst-time propagation delay in the datapath to determine the datapath clock cycle. Complete the micro-operation sequences for all remaining instructions adding connections/multiplexers as needed.

3. EECC550 - Shaaban #3 Lec # 4 Winter 2000 12-13-2000 MIPS Instruction Formats op: Opcode, operation of the instruction. rs, rt, rd: The source and destination register specifiers. shamt: Shift amount. funct: selects the variant of the operation in the “op” field. address / immediate: Address offset or immediate value. target address: Target address of the jump instruction. optarget address 02631 6 bits26 bits oprsrtrdshamtfunct 061116212631 6 bits 5 bits oprsrt immediate 016212631 6 bits16 bits5 bits R-Type I-Type: ALU Load/Store, Branch J-Type: Jumps

4. EECC550 - Shaaban #4 Lec # 4 Winter 2000 12-13-2000 MIPS R-Type (ALU) Instruction Fields op: Opcode, basic operation of the instruction. – For R-Type op = 0 rs: The first register source operand. rt: The second register source operand. rd: The register destination operand. shamt: Shift amount used in constant shift operations. funct: Function, selects the specific variant of operation in the op field. OPrs rt rdshamtfunct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits R-Type: All ALU instructions that use three registers add $1,$2,$3 sub $1,$2,$3 and $1,$2,$3 or $1,$2,$3 Examples: Destination register in rd Operand register in rt Operand register in rs

5. EECC550 - Shaaban #5 Lec # 4 Winter 2000 12-13-2000 MIPS ALU I-Type Instruction Fields I-Type ALU instructions that use two registers and an immediate value Loads/stores, conditional branches. op: Opcode, operation of the instruction. rs: The register source operand. rt: The result destination register. immediate: Constant second operand for ALU instruction. OPrs rt immediate 6 bits 5 bits 5 bits 16 bits add immediate:addi $1,$2,100 and immediateandi $1,$2,10 Examples: Result register in rt Source operand register in rs Constant operand in immediate

6. EECC550 - Shaaban #6 Lec # 4 Winter 2000 12-13-2000 MIPS Load/Store I-Type Instruction Fields op: Opcode, operation of the instruction. –For load op = 35, for store op = 43. rs: The register containing memory base address. rt: For loads, the destination register. For stores, the source register of value to be stored. address: 16-bit memory address offset in bytes added to base register. OPrs rt address 6 bits 5 bits 5 bits 16 bits Store word: sw 500($4), $3 Load word: lw $1, 30($2) Examples: Offset base register in rs source register in rt Destination register in rt Offset base register in rs

7. EECC550 - Shaaban #7 Lec # 4 Winter 2000 12-13-2000 MIPS Branch I-Type Instruction Fields op: Opcode, operation of the instruction. rs: The first register being compared rt: The second register being compared. address: 16-bit memory address branch target offset in words added to PC to form branch address. OPrs rt address 6 bits 5 bits 5 bits 16 bits Branch on equal beq $1,$2,100 Branch on not equal bne $1,$2,100 Examples: Register in rs Register in rt offset in bytes equal to instruction field address x 4

8. EECC550 - Shaaban #8 Lec # 4 Winter 2000 12-13-2000 MIPS J-Type Instruction Fields op: Opcode, operation of the instruction. –Jump j op = 2 –Jump and link jal op = 3 jump target: jump memory address in words. J-Type: Include jump j, jump and link jal OP jump target 6 bits 26 bits Branch on equal j 10000 Branch on not equal jal 10000 Examples: Jump memory address in bytes equal to instruction field jump target x 4

9. EECC550 - Shaaban #9 Lec # 4 Winter 2000 12-13-2000 A Subset of MIPS Instructions ADD and SUB: addU rd, rs, rt subU rd, rs, rt OR Immediate: ori rt, rs, imm16 LOAD and STORE Word lw rt, rs, imm16 sw rt, rs, imm16 BRANCH: beq rs, rt, imm16 oprsrtrdshamtfunct 061116212631 6 bits 5 bits oprsrtimmediate 016212631 6 bits16 bits5 bits oprsrtimmediate 016212631 6 bits16 bits5 bits oprsrtimmediate 016212631 6 bits16 bits5 bits

10. EECC550 - Shaaban #10 Lec # 4 Winter 2000 12-13-2000 Instruction Processing Steps Obtain instruction from program storage Determine instruction type Obtain operands from registers Compute result value or status Store result in register/memory if needed (usually called Write Back). Update program counter to address of next instruction } Common steps for all instructions Instruction Fetch Instruction Decode Execute Result Store Next Instruction

11. EECC550 - Shaaban #11 Lec # 4 Winter 2000 12-13-2000 Overview of MIPS Instruction Micro-operations All instructions go through these two steps: –Send program counter to instruction memory and fetch the instruction. (fetch) –Read one or two registers, using instruction fields. (decode) Load reads one register only. Additional instruction execution actions (execution) depend on the instruction in question, but similarities exist: –All instruction classes use the ALU after reading the registers: Memory reference instructions use it for address calculation. Arithmetic and logic instructions (R-Type), use it for the specified operation. Branches use it for comparison. Additional execution steps where instruction classes differ: –Memory reference instructions: Access memory for a load or store. –Arithmetic and logic instructions: Write ALU result back in register. –Branch instructions: Change next instruction address based on comparison.

12. EECC550 - Shaaban #12 Lec # 4 Winter 2000 12-13-2000 A Single Cycle Implementation Design target : A single-cycle instruction implementation All micro-operations of an instruction are to be carried out in a single system clock cycle.

13. EECC550 - Shaaban #13 Lec # 4 Winter 2000 12-13-2000 Datapath Components Datapath Components Two state elements needed to store and access instructions: 1 Instruction memory: Only read access. No read control signal. 2 Program counter: 32-bit register. Written at end of every clock cycle: No write control signal. 32-bit Adder: To compute the the next instruction address. Instruction Word

14. EECC550 - Shaaban #14 Lec # 4 Winter 2000 12-13-2000 More Datapath Components Register File: Contains all registers. Two read ports and one write port. Register writes by asserting write control signal Writes are edge-triggered. Can read and write to the same register in the same clock cycle. Register File Main ALU

15. EECC550 - Shaaban #15 Lec # 4 Winter 2000 12-13-2000 Register File consists of 32 registers: –Two 32-bit output busses: busA and busB –One 32-bit input bus: busW Register is selected by: –RA (number) selects the register to put on busA (data): busA = R[RA] –RB (number) selects the register to put on busB (data): busB = R[RB] –RW (number) selects the register to be written via busW (data) when Write Enable is 1 Write Enable: R[RW]  busW Clock input (CLK) –The CLK input is a factor ONLY during write operations. –During read operation, it behaves as a combinational logic block: RA or RB valid => busA or busB valid after “access time.” Register File Details Clk busW Write Enable 32 busA 32 busB 555 RWRARB 32 32-bit Registers

16. EECC550 - Shaaban #16 Lec # 4 Winter 2000 12-13-2000 Idealized Memory Memory (idealized) –One input bus: Data In. –One output bus: Data Out. Memory word is selected by: –Address selects the word to put on Data Out bus. –Write Enable = 1: address selects the memory word to be written via the Data In bus. Clock input (CLK): –The CLK input is a factor ONLY during write operation, –During read operation, this memory behaves as a combinational logic block: Address valid => Data Out valid after “access time.” Clk Data In Write Enable 32 DataOut Address

17. EECC550 - Shaaban #17 Lec # 4 Winter 2000 12-13-2000 Instruction Word  Mem[PC]Fetch the instruction PC  PC + 4Increment PC R[rd]  R[rs] + R[rt]Add register rs to register rt result in register rd R-Type Example: Micro-Operation Sequence For ADDU OPrs rt rdshamtfunct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits addU rd, rs, rt

18. EECC550 - Shaaban #18 Lec # 4 Winter 2000 12-13-2000 Building The Datapath Portion of the datapath used for fetching instructions and incrementing the program counter. Instruction Fetch & PC Update:

19. EECC550 - Shaaban #19 Lec # 4 Winter 2000 12-13-2000 Simplified Datapath For R-Type Instructions

20. EECC550 - Shaaban #20 Lec # 4 Winter 2000 12-13-2000 More Detailed Datapath For R-Type Instructions With Control Points Identified 32 Result ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers RsRtRd ALU

21. EECC550 - Shaaban #21 Lec # 4 Winter 2000 12-13-2000 R-Type Register-Register Timing 32 Result ALUct r Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers RsRtRd ALU Clk PC Rs, Rt, Rd, Op, Func Clk-to-Q ALUctr Instruction Memory Access Time Old Value New Value RegWrOld Value New Value Delay through Control Logic busA, B Register File Access Time Old Value New Value busW ALU Delay Old Value New Value Old Value New Value Old Value Register Write Occurs Here

22. EECC550 - Shaaban #22 Lec # 4 Winter 2000 12-13-2000 Instruction Word  Mem[PC]Fetch the instruction PC  PC + 4Increment PC R[rt]  R[rs] OR ZeroExt[imm16]OR register rs with immediate field zero extended to 32 bits, result in register rt Example : Micro-Operation Sequence For ORI Logical Operations with Immediate Example : Micro-Operation Sequence For ORI oprsrtimmediate 016212631 6 bits16 bits5 bits ori rt, rs, imm16

23. EECC550 - Shaaban #23 Lec # 4 Winter 2000 12-13-2000 Datapath For Logical Instructions With Immediate 32 Result ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs RtRd RegDst ZeroExt Mux 32 16 imm16 ALUSrc ALU

24. EECC550 - Shaaban #24 Lec # 4 Winter 2000 12-13-2000 Instruction Word  Mem[PC]Fetch the instruction PC  PC + 4Increment PC R[rt]  Mem[R[rs] + SignExt[imm16]]Immediate field sign extended to 32 bits and added to register rs to form memory load address, word at load address to register rt Example : Micro-Operation Sequence For LW Load Operations Example : Micro-Operation Sequence For LW oprsrtimmediate 016212631 6 bits16 bits5 bits lw rt, rs, imm16

25. EECC550 - Shaaban #25 Lec # 4 Winter 2000 12-13-2000 Additional Datapath Components For Loads & Stores Inputs for address and write (store) data Output for read (load) result 16-bit input sign-extended into a 32-bit value at the output

26. EECC550 - Shaaban #26 Lec # 4 Winter 2000 12-13-2000 Datapath For Loads 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs RtRd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Clk Data In WrEn 32 Adr Data Memory 32 ALU MemWr Mu x W_Src

27. EECC550 - Shaaban #27 Lec # 4 Winter 2000 12-13-2000 Instruction Word  Mem[PC]Fetch the instruction PC  PC + 4Increment PC Mem[R[rs] + SignExt[imm16]]  R[rt] Immediate field sign extended to 32 bits and added to register rs to form memory store address, register rt written to memory at store address. Example : Micro-Operation Sequence For SW Store Operations Example : Micro-Operation Sequence For SW oprsrtimmediate 016212631 6 bits16 bits5 bits sw rt, rs, imm16

28. EECC550 - Shaaban #28 Lec # 4 Winter 2000 12-13-2000 Datapath For Stores ALUSrc ExtOp 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst Extender Mux 32 16 imm16 Clk Data In WrEn 32 Adr Data Memory MemWr ALU 32 Mu x W_Src

29. EECC550 - Shaaban #29 Lec # 4 Winter 2000 12-13-2000 Instruction Word  Mem[PC]Fetch the instruction PC  PC + 4Increment PC Equal  R[rs] == R[rt]Calculate the branch condition if (COND eq 0) PC  PC + 4 + ( SignExt(imm16) x 4 ) Calculate the next instruction’s PC else address PC  PC + 4 Example : Micro-Operation Sequence For BEQ Conditional Branch Example : Micro-Operation Sequence For BEQ oprsrtimmediate 016212631 6 bits16 bits5 bits beqrs, rt, imm16

30. EECC550 - Shaaban #30 Lec # 4 Winter 2000 12-13-2000 Datapath For Branch Instructions ALU to evaluate branch condition Adder to compute branch target: Sum of incremented PC and the sign-extended lower 16-bits on the instruction.

31. EECC550 - Shaaban #31 Lec # 4 Winter 2000 12-13-2000 More Detailed Datapath For Branch Operations Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Equal? Cond 32 imm16 PC Clk 00 Adder Mux Adder 4 nPC_sel PC Ext Instruction Address 32

32. EECC550 - Shaaban #32 Lec # 4 Winter 2000 12-13-2000 Combining The Datapaths For Memory Instructions and R-Type Instructions Highlighted muliplexors and connections added to combine the datapaths of memory and R-Type instructions into one datapath

33. EECC550 - Shaaban #33 Lec # 4 Winter 2000 12-13-2000 Instruction Fetch Datapath Added to ALU R-Type and Memory Instructions Datapath

34. EECC550 - Shaaban #34 Lec # 4 Winter 2000 12-13-2000 A Simple Datapath For The MIPS Architecture Datapath of branches and a program counter multiplexor are added. Resulting datapath can execute in a single cycle the basic MIPS instruction: - load/store word - ALU operations - Branches

35. EECC550 - Shaaban #35 Lec # 4 Winter 2000 12-13-2000 Single Cycle MIPS Datapath Necessary multiplexors and control lines are identified here:

36. EECC550 - Shaaban #36 Lec # 4 Winter 2000 12-13-2000 Putting It All Together: A Single Cycle Datapath

37. EECC550 - Shaaban #37 Lec # 4 Winter 2000 12-13-2000 Instruction Word  Mem[PC]Fetch the instruction PC  PC + 4Increment PC PC  PC(31-28),jump_target,00 Update PC with jump address : Micro-Operation Sequence For Jump: J Adding Support For Jump : Micro-Operation Sequence For Jump: J OP Jump_target 6 bits 26 bits j jump_target

38. EECC550 - Shaaban #38 Lec # 4 Winter 2000 12-13-2000 Datapath For Jump 32 PC Clk 00 Mux nPC_sel imm16 Adder 4 PC Ext Next Instruction Address Mux JUMP Shift left 2 jump_target Instruction(15-0) Instruction(25-0) 32 26 PC+4(31-28) 28 32 4

39. EECC550 - Shaaban #39 Lec # 4 Winter 2000 12-13-2000 RegDst ALUctr ALUSrc MemtoReg Equal Instruction Imm16RdRsRt Adr Instruction Memory DATA PATH ExtOp MemWr Control Unit Op Fun nPC_sel RegWr Jump_target Jump

40. EECC550 - Shaaban #40 Lec # 4 Winter 2000 12-13-2000 Single Cycle MIPS Datapath Extended To Handle Jump with Control Unit Added

41. EECC550 - Shaaban #41 Lec # 4 Winter 2000 12-13-2000 Control Signal Generation addsuborilwswbeqjump RegDst ALUSrc MemtoReg RegWrite MemWrite nPCsel Jump ExtOp ALUctr 1 0 0 1 0 0 0 x Add 1 0 0 1 0 0 0 x Subtract 0 1 0 1 0 0 0 0 Or 0 1 1 1 0 0 0 1 Add x 1 x 0 1 0 0 1 x 0 x 0 0 1 0 x Subtract x x x 0 0 0 1 x xxx func op00 0000 00 110110 001110 101100 010000 0010 Appendix A 10 0000See10 0010Don’t Care

42. EECC550 - Shaaban #42 Lec # 4 Winter 2000 12-13-2000 The Concept of Local Decoding Main Control op 6 ALU Control (Local) func N 6 ALUop ALUctr 3 ALU

43. EECC550 - Shaaban #43 Lec # 4 Winter 2000 12-13-2000 Local Decoding of “func” Field R-typeorilwswbeqjump ALUop (Symbolic)“R-type”OrAdd Subtract xxx ALUop 1 000 100 00 0 01 xxx Main Control op 6 ALU Control (Local) func N 6 ALUop ALUctr 3 funct Instruction Operation 10 0000 10 0010 10 0100 10 0101 10 1010 add subtract and or set-on-less-than ALUctr ALU Operation 000 001 010 110 111 Add Subtract And Or Set-on-less-than ALUctr ALU

44. EECC550 - Shaaban #44 Lec # 4 Winter 2000 12-13-2000 The Truth Table for ALUctr R-typeorilwswbeq ALUop (Symbolic) “R-type”OrAdd Subtract ALUop 1 000 100 00 0 01 funct Instruction Op. 0000 0010 0100 0101 1010 add subtract and or set-on-less-than

45. EECC550 - Shaaban #45 Lec # 4 Winter 2000 12-13-2000 The Truth Table For The Main Control

46. EECC550 - Shaaban #46 Lec # 4 Winter 2000 12-13-2000 Example: RegWrite Logic Equation R-typeorilwswbeqjump RegWrite111000 op00 000000 110110 001110 101100 010000 0010 RegWrite = R-type + ori + lw = !op & !op & !op & !op & !op & !op (R-type) + !op & !op & op & op & !op & op (ori) + op & !op & !op & !op & op & op (lw) op.... op.. op.. op.. op.. R-typeorilwswbeqjump RegWrite

47. EECC550 - Shaaban #47 Lec # 4 Winter 2000 12-13-2000 PLA Implementation of the Main Control op.... op.. op.. op.. op.. R-typeorilwswbeqjump RegWrite ALUSrc MemtoReg MemWrite Branch Jump RegDst ExtOp ALUop

48. EECC550 - Shaaban #48 Lec # 4 Winter 2000 12-13-2000 Clk PC Rs, Rt, Rd, Op, Func Clk-to-Q ALUctr Instruction Memoey Access Time Old ValueNew Value RegWrOld ValueNew Value Delay through Control Logic busA Register File Access Time Old ValueNew Value busB ALU Delay Old ValueNew Value Old ValueNew Value Old Value ExtOpOld ValueNew Value ALUSrcOld ValueNew Value MemtoRegOld ValueNew Value AddressOld ValueNew Value busWOld ValueNew Delay through Extender & Mux Register Write Occurs Data Memory Access Time Worst Case Timing (Load)

49. EECC550 - Shaaban #49 Lec # 4 Winter 2000 12-13-2000 Instruction Timing Comparison PCInst Memory mux ALUData Mem mux PCReg FileInst Memory mux ALU mux PCInst Memory mux ALUData Mem PCInst Memorycmp mux Reg File Arithmetic & Logical Load Store Branch Critical Path setup

50. EECC550 - Shaaban #50 Lec # 4 Winter 2000 12-13-2000 Drawback of Single Cycle Processor Long cycle time: –Cycle time must be long enough for the load instruction: PC’s Clock -to-Q + Instruction Memory Access Time + Register File Access Time + ALU Delay (address calculation) + Data Memory Access Time + Register File Setup Time + Clock Skew All instructions must take as much time as the slowest –Cycle time for load is longer than needed for all other instructions. Real memory is not as well-behaved as idealized memory –Cannot always complete data access in one (short) cycle.