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Update on JEM FPGA coding
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Carsten NödingJohannes Gutenberg-Universität Mainz JEM block diagramm
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Carsten NödingJohannes Gutenberg-Universität Mainz Input FPGA Changes since Birmingham Meeting: 256 slices deep playback memory can be written via consecutive single word transfers and read back code clean-up
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Carsten NödingJohannes Gutenberg-Universität Mainz Main Processor
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Carsten NödingJohannes Gutenberg-Universität Mainz E T,miss, E T
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Carsten NödingJohannes Gutenberg-Universität Mainz Main Processor (1) Changes since Birmingham Meeting (only RTDP of energy tree): code clean-up Past: Conversion into E X and E Y was done in 16 LUT based multipliers using ROMs Only changeable by loading a new configuration Handling of INIT values for LUTs is annoying Latency of RTDP: 3 bunch crossings (@41.4 MHz, 25 % logic resources XCV600E-7-FG680C) [Logic resources needed for jet tree: 50-60 %] Present: Multiplication is done using Block SelectRAM capabilities of Virtex-E Changeable via consecutive VME read/write access Easier handling, code easier to understand Latency: 4 bunch crossing (@45 MHz, 15 % logic resources of XCV600E- 7-FG680C)
![Carsten NödingJohannes Gutenberg-Universität Mainz Main Processor (1) Changes since Birmingham Meeting (only RTDP of energy tree): code clean-up Past: Conversion into E X and E Y was done in 16 LUT based multipliers using ROMs Only changeable by loading a new configuration Handling of INIT values for LUTs is annoying Latency of RTDP: 3 bunch crossings MHz, 25 % logic resources XCV600E-7-FG680C) [Logic resources needed for jet tree: %] Present: Multiplication is done using Block SelectRAM capabilities of Virtex-E Changeable via consecutive VME read/write access Easier handling, code easier to understand Latency: 4 bunch crossing MHz, 15 % logic resources of XCV600E- 7-FG680C)](http://images.slideplayer.com./16/5214862/slides/slide_6.jpg "Carsten NödingJohannes Gutenberg-Universität Mainz Main Processor (1) Changes since Birmingham Meeting (only RTDP of energy tree): code clean-up Past: Conversion into E X and E Y was done in 16 LUT based multipliers using ROMs Only changeable by loading a new configuration Handling of INIT values for LUTs is annoying Latency of RTDP: 3 bunch crossings MHz, 25 % logic resources XCV600E-7-FG680C) [Logic resources needed for jet tree: %] Present: Multiplication is done using Block SelectRAM capabilities of Virtex-E Changeable via consecutive VME read/write access Easier handling, code easier to understand Latency: 4 bunch crossing MHz, 15 % logic resources of XCV600E- 7-FG680C)")
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Carsten NödingJohannes Gutenberg-Universität Mainz Main Processor (2) Future: Use Virtex-II device as Main Processor: Multiplication can done using embedded 18bit by 18bit multipliers Accuracy is not worsened Code can be easily adapted (just throw away half of it) Latency: 2.5 bunch crossings
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Carsten NödingJohannes Gutenberg-Universität Mainz Reorganisation of JEM Programming Model Changes since Birmingham Meeting: Added gaps in register offsets (especially around blocks of related ones, eg. jet thresholds) things can be changed in the future without having to change the offsets used in any existing software registers which belong together start at some nice boundary Module ID words start at address 0 of the module Added multiplication registers to store E T sin() and E T cos() results in BlockRAMs (Virtex-E) same register can be used for storing sin() and cos() in Virtex-II devices “separate registers for separate things” Programming Model has been approved by Murrough Current version can be found in the latest JEM PDR available on the web
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Carsten NödingJohannes Gutenberg-Universität Mainz Outlook Main task now: Test of JEM prototype
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