1. Performed by: Guy Zur, Eithan Nadir Instructor: Igal Kogan Cooperated with: המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering דו ” ח סיכום פרויקט סופי Subject: Project name סמסטר אביב תשס " ה 1

2. Abstract המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 2 The project deals with the design of generic system for testing global imaging units. The project attempts to design a general unit which receives data from Ethernet connection and transmits it to a DUT,, also to receive the real time video data, process it and deliver it to a VGA monitor. While working on a project we have encountered some obstacles and were forced to change our approach in solving the problem. In this book we've described our goals and our ways of dealing with the problems. The system is implemented on the Xilinx XUPV2P board, featuring the Xilinx Virtex II Pro FPGA. The main CPU will be one of the 2 embedded PPC405 CPUs.

3. System description המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3 General Tester – CoreGen Controller This is the core of the project we need to transmit (time slot) data through the Ethernet and store it in the ddr. Later on extract the data from it. The following design was proposed and fulfilled. Build a general data generator in order to make a Device/digital camera work. The date received from the Ethernet contains snapshots of the signals that are needed to be generated to the device, in order to make it function properly. The output data from the device is then collected and delivered to the xsga controller. A simple picture algorithm should be done. The data, processed and fixed is then transmitted to an xsga screen of 800x600 pixles.

4. 4 System description המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3 General Tester – DDR-PLB Controller We decided to change the strategy above, instead of using a DMA, we will use the PPC as the DMA controller. The fifo of the Control unit produce an interrupt- according to the interrupt the system will then fetch the next streaming data from the memory.

5. 5 System description המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3 Transmit a Bitmap Picture Over the Ethernet After the previous problems we tried another attitude. Instead of using our xsga controller we will use xilinx’s vga IP.

6. 6 System description המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3 Streaming Data transmitted using the svga controller In this project we have been asked to design and build a custom IP that receive data from the OPB interface. And deliver it to the screen using xsga controller.

7. Specification המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Hardware Software 4 Each attitude toward the solution has its own set of hardware. But in general we used: PPC405;Ethernet controller; opb; plb; vga tft controller; Uart; ;DDR controller; our custom made IPs We relayed on the default drivers. We used xilinx’s Xilnet libraries for ethernet support and standard libraries for I/O.

8. System Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 5

9. FPGA Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 DDR-PLB Controller Bitmap Picture Over the Ethernet Streaming data