1. Chapter 7. Basic Processing Unit

2. Overview Instruction Set Processor (ISP) Central Processing Unit (CPU)
A typical computing task consists of a series of steps specified by a sequence of machine instructions that constitute a program.
An instruction is executed by carrying out a sequence of more rudimentary operations.

3. Some Fundamental Concepts

4. Fundamental Concepts
Processor fetches one instruction at a time and perform the operation specified.
Instructions are fetched from successive memory locations until a branch or a jump instruction is encountered.
Processor keeps track of the address of the memory location containing the next instruction to be fetched using Program Counter (PC).
Instruction Register (IR)

5. Executing an Instruction
Fetch the contents of the memory location pointed to by the PC. The contents of this location are loaded into the IR (fetch phase).
IR ← [[PC]]
Assuming that the memory is byte addressable, increment the contents of the PC by 4 (fetch phase).
PC ← [PC] + 4
Carry out the actions specified by the instruction in the IR (execution phase).

6. Processor Organization
MDR HAS TWO INPUTS AND TWO OUTPUTS
Datapath
Textbook Page 413

7. Executing an Instruction
Transfer a word of data from one processor register to another or to the ALU.
Perform an arithmetic or a logic operation and store the result in a processor register.
Fetch the contents of a given memory location and load them into a processor register.
Store a word of data from a processor register into a given memory location.

8. Register Transfers B A Z
ALU Y in
out R i b us
Internal processor
Constant 4
MUX
Figure Input and output gating for the registers in Figure 7.1.
Select

9. Figure 7.3. Input and output gating for one register bit.
Register Transfers
All operations and data transfers are controlled by the processor clock.
Figure Input and output gating for one register bit.

10. Performing an Arithmetic or Logic Operation
The ALU is a combinational circuit that has no internal storage.
ALU gets the two operands from MUX and bus. The result is temporarily stored in register Z.
What is the sequence of operations to add the contents of register R1 to those of R2 and store the result in R3?
R1out, Yin
R2out, SelectY, Add, Zin
Zout, R3in

11. Fetching a Word from Memory
Address into MAR; issue Read operation; data into MDR.
Figure Connection and control signals for register MDR.

12. Fetching a Word from Memory
The response time of each memory access varies (cache miss, memory-mapped I/O,…).
To accommodate this, the processor waits until it receives an indication that the requested operation has been completed (Memory-Function-Completed, MFC).
Move (R1), R2
MAR ← [R1]
Start a Read operation on the memory bus
Wait for the MFC response from the memory
Load MDR from the memory bus
R2 ← [MDR]

13. Timing MAR ← [R1] Assume MAR is always available on the address lines
of the memory bus.
Start a Read operation on the memory bus
Wait for the MFC response from the memory
Load MDR from the memory bus
R2 ← [MDR]

14. Execution of a Complete Instruction
Add (R3), R1
Fetch the instruction
Fetch the first operand (the contents of the memory location pointed to by R3)
Perform the addition
Load the result into R1

15. Architecture B A Z
ALU Y in
out R i b us
Internal processor
Constant 4
MUX
Figure Input and output gating for the registers in Figure 7.1.
Select

16. Execution of a Complete Instruction
Add (R3), R1

17. Execution of Branch Instructions
A branch instruction replaces the contents of PC with the branch target address, which is usually obtained by adding an offset X given in the branch instruction.
The offset X is usually the difference between the branch target address and the address immediately following the branch instruction.
Conditional branch

18. Execution of Branch Instructions
Step
Action 1 PC ,
MAR ,
Read,
Select4,
Add, Z
out in in 2 Z , PC , Y ,
WMF C
out in in 3
MDR , IR
out in 4
Offset-field-of-IR ,
Add, Z
out in 5 Z , PC ,
End
out in
Figure Control sequence for an unconditional branch instruction.

19. Multiple-Bus Organization

20. Multiple-Bus Organization
Add R4, R5, R6
Step
Action 1 PC ,
R=B,
MAR ,
Read,
IncPC
out in 2
WMF C 3
MDR ,
R=B, IR
outB in 4 R4 , R5 ,
SelectA,
Add, R6 ,
End
outA
outB in
Figure 7.9. Control sequence for the instruction. Add R4,R5,R6,
for the three-bus organization in Figure 7.8.

21. Quiz What is the control sequence for execution of the instruction
Add R1, R2
including the instruction fetch phase? (Assume single bus architecture)

22. Hardwired Control

23. Overview
To execute instructions, the processor must have some means of generating the control signals needed in the proper sequence.
Two categories: hardwired control and microprogrammed control
Hardwired system can operate at high speed; but with little flexibility.

24. Control Unit Organization
CLK
Control step
Clock
counter
External
inputs
Decoder/ IR
encoder
Condition
codes
Control signals
Figure Control unit organization.

25. Detailed Block Description

26. Generating Zin Zin = T1 + T6 • ADD + T4 • BR + …
Branch
Add T T 4 6 T 1
Figure Generation of the Zin control signal for the processor in Figure 7.1.

27. Generating End
End = T7 • ADD + T5 • BR + (T5 • N + T4 • N) • BRN +…

28. A Complete Processor

29. Microprogrammed Control

30. Overview
Control signals are generated by a program similar to machine language programs.
Control Word (CW); microroutine; microinstruction

31. Overview

32. Overview Control store One function cannot be carried
out by this simple
organization.

33. Overview
The previous organization cannot handle the situation when the control unit is required to check the status of the condition codes or external inputs to choose between alternative courses of action.
Use conditional branch microinstruction.
Address
Microinstruction PC ,
MAR ,
Read,
Select4,
Add, Z
out in in 1 Z , PC , Y ,
WMF C
out in in 2
MDR , IR
out in 3
Branch to
starting
address of
appropriate
microroutine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 If
N=0,
then
branch to
microinstruction 26
Offset-field-of-IR ,
SelectY,
Add, Z
out in 27 Z , PC ,
End
out in
Figure Microroutine for the instruction Branch<0.

34. Overview Figure 7.18. Organization of the control unit to allow
External
inputs
Starting and
Condition IR
branch address
codes
generator
Clock m P C
Control CW
store
Figure Organization of the control unit to allow
conditional branching in the microprogram.

35. Microinstructions
A straightforward way to structure microinstructions is to assign one bit position to each control signal.
However, this is very inefficient.
The length can be reduced: most signals are not needed simultaneously, and many signals are mutually exclusive.
All mutually exclusive signals are placed in the same group in binary coding.

36. Partial Format for the Microinstructions
What is the price paid for
this scheme?

37. Further Improvement
Enumerate the patterns of required signals in all possible microinstructions. Each meaningful combination of active control signals can then be assigned a distinct code.
Vertical organization
Horizontal organization

38. Microprogram Sequencing
If all microprograms require only straightforward sequential execution of microinstructions except for branches, letting a μPC governs the sequencing would be efficient.
However, two disadvantages:
Having a separate microroutine for each machine instruction results in a large total number of microinstructions and a large control store.
Longer execution time because it takes more time to carry out the required branches.
Example: Add src, Rdst
Four addressing modes: register, autoincrement, autodecrement, and indexed (with indirect forms).

39. - Bit-ORing
- Wide-Branch Addressing
- WMFC

40. 101 (from Instruction decoder);
Mode
Contents of IR
OP code 1
Rsrc
Rdst 11 10 8 7 4 3
Address
Microinstruction
(octal)
000 PC
, MAR
, Read, Select 4
, Add, Z
out in in
001 Z
, PC
, Y
, WMFC
out in in
002
MDR
, IR
out in
003 m
Branch { m PC
101 (from Instruction decoder); m PC
[IR ]; m PC
[IR ] ×
[IR ] ×
[IR ]}
5,4
10,9 3 10 9 8
121
Rsrc
, MAR
, Read, Select4, Add, Z
out in in
122 Z
, Rsrc
out in
123 m
Branch { m PC
170; m PC
[IR 8
]}, WMFC
170
MDR
, MAR
, Read, WMFC
out in
171
MDR
, Y
out in
172
Rdst
, SelectY
, Add, Z
out in
173 Z
, Rdst
, End
out in
Figure 7.21.
Microinstruction for Add (Rsrc)+,Rdst.
Note:
Microinstruction at location 170 is not executed for this addressing mode.

41. Microinstructions with Next-Address Field
The microprogram we discussed requires several branch microinstructions, which perform no useful operation in the datapath.
A powerful alternative approach is to include an address field as a part of every microinstruction to indicate the location of the next microinstruction to be fetched.
Pros: separate branch microinstructions are virtually eliminated; few limitations in assigning addresses to microinstructions.
Cons: additional bits for the address field (around 1/6)

42. Microinstructions with Next-Address Field

44. Implementation of the Microroutine

46. bit-ORing

47. Further Discussions
Prefetching
Emulation