1. A Probabilistic Method to Determine the Minimum Leakage Vector for Combinational Designs Kanupriya Gulati Nikhil Jayakumar Sunil P. Khatri Department of Electrical & Computer Engineering Texas A&M University, College Station, TX-77843

2. Hence it is desirable to set every gate to its minimal leakage state. Not always possible Logical inter-dependencies of the gates’ inputs. Finding the input vector to minimize the circuit leakage : Input Vector Control (IVC). Motivation InputLeakage (A) 0001.37389 e -10 0012.69965 e -10 0102.70326 e -10 0114.96216 e -09 1002.62308 e -10 1012.67509 e -09 1102.51066 e -09 1111.01162 e -08 Leakage of a NAND3 gate Sub Threshold Leakage Current (I ds ) Magnitude of ‘Leakage Currents’ depend on the ‘Input Vector’.

3. Overview of our Approach First compute signal probabilities for all nodes assuming primary input signal probabilities are 0.5. –Heuristically adjust for reconvergence. Select best “candidate” gate to set to low leakage state in a given iteration. –Gate that is probabilistically most likely to result in the largest leakage reduction. Assign the selected gate its best state, such that the leakage of the selected gate is probabilistically minimized. –All other gates which are newly implied by the state just selected are accounted for when making this decision.

4. Overview of our Approach Check if the logic values set when setting a gate to its low leakage state are satisfiable. –Call a SAT solver every p iterations. –Undo assignments in last p iterations if unsatisfiable and make a different selection for the iteration that caused unsatisfiable condition. After any iteration, adjust gate probabilities to account for nodes whose logic values have been set. Fixed number of passes made for the circuit with above steps applied succesively. –Each pass is more “lenient” in setting a node to a logic value v when its signal probability deviates from v. –Last pass is most lenient – allows any deviation from v to be accepted.

5. Adjustment Heuristic for Reconvergent Fanouts XVWZ 0100 1010 P(Z) new = 0 0.25 0.75 0.1875 Z Adj Factor = P(Z) new - P(Z) = - 1 P(Z) P(Z) = 0.1875 Propagate probabilities assuming P(X) = 0 and P(X) = 1 to calculate reconvergence adjustment factor. P(Z) adj = P(Z) * (1+Z Adj Factor )

6. p i – probability that gate is in state i l i – leakage in state i l i max – maximum leakage of the gate l i min – minimum leakage of the gate Finding Best Candidate Gate (l i max – l i min ) term ensures that gates with large leakage ranges are favored. Choose gate with highest C. Find best candidate gate whose input we would like to finalize. Rank gates by probability criterion C. Gates with high probability of being in a high leakage state are assigned a higher rank.

7. Finding the best (minimum) leakage state for selected gate G. Account for leakages for all gates n whose states become fully assigned due to assigning of the state of G. - Modified formula for L to allow biasing towards lower leakage (use higher β) or towards lower deviation (use higher γ) d j – deviation of values assigned to gate inputs from their probabilistic values. l j – leakage in state j j – set of states of all gates that are fully assigned Finding Best Leakage State

8. Accepting the State Assignment Test if implications of assignment are within a margin(m i ). - say m i = 0.5, probability = 0.3 and implied node value is logic 1. Then (1-0.3) > m i, hence reject assignment. Test if the circuit with these assignments is satisfiable. Update probabilities of all gates affected. Until the SAT solver sanctions these assignments, labeled as gold_value, and then platinum_value. Over iterations the margin (m i ) for accepting an assignment is relaxed. Stop when all primary inputs have been assigned a state. Implied node probabilities are adjusted to reflect newly computed implications. If node is set to 1, probability is set to (1-α). If node is set to 0, probability is set to α. Accepting Leakage States and Endgame

9. Used MCNC 91 benchmark designs using 0.1μ library with 13 gates. Number of inputs (library gates) between 1 & 4. Ran technology independent logic optimizations (script_rugged in SIS). Mapped them for delay. PL min technique is implemented in SIS. Tried the following 3 methods. Experimental Setup Commonly used Figure of Merit: Our new Figure of Merit:

10. Exhaustive and Estimated Leakages for small circuits in nA. Results - Small circuits - For small circuits the minimum and maximum leakage values were found through exhaustive simulation of all primary input vectors.

11. Results – Large Circuits For large circuits, the minimum and maximum leakage values were found by simulating 10000 distinct random input vectors.

12. Developed a probabilistic method to determine IVC. Method is fast, flexible and provides accurate results. For small examples, found leakage values 5.3% off from minimum leakage (exact). For large examples, found leakage values 3.7% off the minimum leakage (random 10,000 vectors). Runtimes of the method are much lower than existing techniques which produce similar quality results. Conclusions

13. Leakage for Large Circuits in nA Results - Large circuits

14. Algorithm for determining IVC: … (contd)

15. Algorithm for determining IVC: (contd)