1. Contemporary Logic Design FSM Optimization © R.H. Katz Transparency No. 17-1 Chapter #9: Finite State Machine 9.4 Choosing Flip-Flops 9.5 Machine Partitioning

2. Contemporary Logic Design FSM Optimization © R.H. Katz Transparency No. 17-2 9.4 Choice of Flipflops J-K FFs: reduce gate count, increase # of connections D FFs: simplify implementation process, decrease # of connections, well-suited for VLSI implementation Procedure: 1.Given state assignments, derive the next state maps from the state transition table 2.Remap the next state maps given excitation tables for a given FF 3.Minimize the remapped next state function

3. Contemporary Logic Design FSM Optimization © R.H. Katz Transparency No. 17-3 Example FSM Specification: 4-bit sequence detector Single input X, output Z Taking inputs grouped four at a time, output 1 if last four inputs were the string 1010 or 0110 Example I/O Behavior: X = 0010 0110 1100 1010 0011... Z = 0000 0001 0000 0001 0000... Choice of Flipflops The inputs have been written to lag behind the outputs.

4. Contemporary Logic Design FSM Optimization © R.H. Katz Transparency No. 17-4 Choice of Flipflops Examples 4 bit Sequence Detector using NOVA derived state assignment Encoded State Transition Table Encoded Next State Map Present State 000 (S 0 ) 011 (S 1 ) 010 (S 2 ) 101 (S 3 ') 111 (S 4 ') 100 (S 7 ') 110 (S 10 ') I=0 011 (S 1 ) 101 (S 3 ') 111 (S 4 ') 100 (S 7 ') 000 I=1 010 (S 2 ) 111 (S 4 ') 101 (S 3 ') 100 (S 7 ') 110 ( S ) 0 000 Next StateOutput I=0 0 0 0 0 0 0 1 I=1 0 0 0 0 0 0 0 000 Q2 Q1 Q0

5. Contemporary Logic Design FSM Optimization © R.H. Katz Transparency No. 17-5 Choice of Flipflops D FF Implementation D = Q2 Q1 + Q0 Q2+ D = Q1 Q0 I + Q2 Q0 I + Q2 Q1 Q1+ D = Q2 Q1 + Q2 I Q0+ 6 product terms 15 literals 3- 3-inputs gates 5- 2-inputs gates 4- inverters 12 gates

6. Contemporary Logic Design FSM Optimization © R.H. Katz Transparency No. 17-6 Choice of Flipflops J-K Implementation Remapped Next State Table

7. Contemporary Logic Design FSM Optimization © R.H. Katz Transparency No. 17-7 Choice of Flipflops J-K Implementation (continued) J = Q1 K = Q0 J = Q2 K = Q0 I + Q0 I + Q2 Q0 J = Q2 Q1 + Q2 I K = Q2 Q2+ Q1+ Q0+ 9 unique terms 14 literals Q 0 I Q 2 Q 1 000111 10 00 01 11 10 00X X 1111 X XX XX X X X Q 2 Q 1 Q 0 I 00011110 00 01 11 10 XXX X XXXX 1100 11 00 Q 2 Q 1 000111 10 00 01 11 10 11 XX X X XX XX XX 0000 Q 0 I Q 2 Q 1 000111 10 00 01 11 10 X X X X 01 01 1 101 XXXX Q 0 I Q 0 I Q 0 I Q 2 Q 1 Q 2 Q 1 00011110 00 01 11 10 1 0 X X 11 X X 00 XX 0 0X X X XX X X X 0 0 X X 11 XX11 00011110 00 01 11 10 K Q1 + K Q2 + J Q1 + J Q2 + J Q0 + K 1 - 3-inputs gate 6- 2-inputs gates 3- inverters ====> 10 gates

8. Contemporary Logic Design FSM Optimization © R.H. Katz Transparency No. 17-8 9.5 Finite State Machine Partitioning Why Partition? mapping FSMs onto programmable logic components (e.g. PALs): limited number of input/output pins limited number of product terms or other programmable resources Example of Input/Output Partitioning: 5 outputs depend on 15 inputs 5 outputs depend on different overlapping set of 15 inputs

9. Contemporary Logic Design FSM Optimization © R.H. Katz Transparency No. 17-9 Finite State Machine Partitioning Introduction of Idle States Before Partitioning Ci -- Boolean Condition

10. Contemporary Logic Design FSM Optimization © R.H. Katz Transparency No. 17-10 Finite State Machine Partitioning If we partition the state diagrams, but a transition must take place between the two pieces. We must introduce idle states to synchronize the activity between the two finite state machines For example, the machine at the left hands control off to the machine on the right, when a transition from S1 to S6 takes place. The left machine must idle in some new state until it regains control, such as when there is a transition from S6 back to S1. In this event, the machine on the right must remain idle until it regains control.

11. Contemporary Logic Design FSM Optimization © R.H. Katz Transparency No. 17-11 Finite State Machine Partitioning After Partitioning Introduction of Idle States Two new states SA and SB are introduced. For the state sequence S1 to S6 and back to S1. Initially the machines are in state S1 and SB. If condition C1 is true, then the left-hand state machine exits S1 and enters its idle state, SA. At the same time, the left-hand state machine exits SB and enters S6.

12. Contemporary Logic Design FSM Optimization © R.H. Katz Transparency No. 17-12 Finite State Machine Partitioning Rules for Partitioning Rule #1: Source State Transformation; SA is the Idle State Rule #2: Destination State Transformation

13. Contemporary Logic Design FSM Optimization © R.H. Katz Transparency No. 17-13 Finite State Machine Partitioning Rules for Partitioning Rule #3: Multiple Transitions with Same Source or Destination Rule #4: Hold Condition for Idle State Source Destination from idle state S A

14. Contemporary Logic Design FSM Optimization © R.H. Katz Transparency No. 17-14 Finite State Machine Partitioning Another Example 6 state up/down counter building block has 2 FFs + combinational logic ==> Hence use 2 partitions with 4 states each (3 states plus the idle state)

15. Contemporary Logic Design FSM Optimization © R.H. Katz Transparency No. 17-15 Finite State Machine Partitioning 6 State Up/Down Counter Introduction of the two idle state SA, SB Count sequence S0, S1, S2, S3, S4, S5: S2 goes to SA and holds, leaves after S5 S5 goes to SB and holds, leaves after S2 Down sequence is similar

16. Contemporary Logic Design FSM Optimization © R.H. Katz Transparency No. 17-16 HW #17 -- Sections 9.4 & 9.5