1. [M2] Traffic Control Group 2 Chun Han Chen Timothy Kwan Tom Bolds Shang Yi Lin Manager Randal Hong Wed. Oct. 20 Overall Project Objective : Dynamic Control The Traffic Lights

2. Status  Design Proposal  Chip Architecture  Behavioral Verilog Implementation  Size estimates  Floorplanning  Behavioral Verilog simulated  Gate Level Design  Component Layout/Simulation  Chip Layout  Complete Simulation

3. Data Input Initial Values Clock Operation T, Left-Turn Counter R, r, R_ L, r_ l Flow Control FSM Light Contro l FSM Selection

4. Block (# used)Transistor CountsSize Estimates (um) Register ( 13 )680425792.6 MUX ( 12 )930035254.4 Accumulator ( 4 )18487005.4 ALU ( 1 )484818377.8 Comparator 8-bits ( 1 )240909.8 Flow Control FSM8322790.0 Light Control FSM8822957.7 Total~ 24754~ 93087.3 Block Size Estimates 530um x 460 um ~ 1.15 : 1 aspect ratio.243 mm^2 area.11 Transistor Density

5. Current Version Wire routing on each block

6. Refined Floorplan

7. [New] Wire Pre-Decision on Block M3 & M4Selection Signal M1 & M2Multipliers M1 & M2Adder/Subtrator M1 & M2Accumulator M1 & M2 & M3 & M411-bit Reg.+12-bit Reg. M1 & M2Register M1 & M2 & M3 & M42:1 MUX Array (x110) M1 & M2 & M316:1,2:1 MUX/DEMUX Metal Layers That Have Been UsedBlock

8. Layout Info.  For each block that exists (FSMs, Add/Mult), each person will determine their own layout sizes for each gate.  For the Add/Mult, the height of the largest Full Adder will be used as the baseline for all the other gates in it.

9. 1-bit Register VDD VSS D Clear Set Clk Clk_b Q

10. 11-bit Register

11. Issues  We assume simulation technology works, perhaps we just don ’ t know how to use it correctly?