1. Timing Analysis of Cyclic Combinational Circuits Marc D. Riedel and Jehoshua Bruck California Institute of Technology IWLS, Temecula Creek, CA, June 4, 2004 Marrella splendensCyclic circuit

2. inputsoutputs The current outputs depend only on the current inputs. Combinational Circuits combinational logic

3. Generally acyclic (i.e., feed-forward) structures. Combinational Circuits x y x y z z c s AND OR AND XOR

4. Cyclic Combinational Circuits a b x c d x AND OR AND OR Circuit is cyclic yet combinational; computes functions and with 6 gates. An acyclic circuit computing these functions requires 8 gates.

5. Timing Analysis Predicated on a topological ordering. l 1 = 1 level: l 2 = 1 x y x y z z c s g1g1 g4g4 g3g3 g2g2 g5g5 l 3 = 2 l 5 = 2 l 4 = 3

6. z 1010 1010 1010 1010 1010 1212 0202 1212 Timing Analysis Predicated on a topological ordering. 1 0101 x y x y z c s arrival times 1010 (assume a delay bound of 1 time unit for each gate) l 1 = 1 l 2 = 1 g4g4 g3g3 g2g2 g5g5 l 3 = 2 l 5 = 2 l 4 = 3 g1g1 level:

7. Cyclic Combinational Circuits a b x c d x No topological ordering. How can we perform timing analysis? AND OR AND OR

8. Cyclic Combinational Circuits a b x c d x 1010 1010 0 1010 1010 0 1 1212 1313 1414 1515 1616 AND OR AND OR No topological ordering. How can we perform timing analysis?

9. Algorithms for functional analysis (IWLS’03); Strategies for synthesis (DAC’03). In trials on benchmark circuits, cyclic optimizations reduced the area of by as much as 30% In previous papers, we presented: Prior Work

10. Optimization for Area Number of NAND2/NOR2 gates in Berkeley SIS vs. CYCLIFYsolutions BenchmarkBerkeley SISCaltech CYCLIFYImprovement 5xp120318210.34% ex619415221.65% planet9438895.73% s3862312223.90% bw30225515.56% cse3443294.36% pma4093933.91% s5105144836.03% duke284767320.54% styr85875811.66% s1488108410037.47% application of “script.rugged” and mapping

11. An algorithm for timing analysis. Synthesis results, with optimization jointly targeting area and delay. In trials on benchmarks circuits, cyclic optimizations simultaneously reduced the area by up to 10% and the delay by up to 25%. In this paper, we discuss: Contributions

12. cyclic circuit acyclic circuit Related Work Their approach: identify equivalent acyclic circuits. Malik (1994), Hsu, Sun and Du (1998), and Edwards (2003) considered analysis techniques for cyclic circuits. inputsoutputs Unravelling cyclic circuits this way is a difficult task. minimum-cut feedback set

13. Our Approach Perform event propagation, directly on a cyclic circuit. outputs inputs cyclic circuit 1010 1010 0 1010 0 1313 1616

14. Our Approach Perform event propagation, directly on a cyclic circuit. [b]0[b]0 [c]0[c]0 [a]0[a]0 [x]0[x]0 [d]0[d]0 f 2 =[d+c(x+ba))] 6 f 1 =[b(a+x(c+d))] 6 Compute events symbolically, with BDDs. cyclic circuit

15. Circuit Model Perform static analysis in the “floating-mode”. At the outset: all wires are assumed to have unknown/undefined values ( ). the primary inputs assume definite values in {0, 1}. a “controlling” input full set of “non-controlling” inputs unknown/undefined output

16. Circuit Model During the analysis, only signals driven (directly or indirectly) by the primary inputs are assigned definite values. 1    ORAND   Perform static analysis in the “floating-mode”. At the outset: all wires are assumed to have unknown/undefined values ( ). the primary inputs assume definite values in {0, 1}.

17. Circuit Model AND Up-bounded inertial delay model. each gate has delay in [ 0, t d ] Ensures monotone speed-up property.

18. Circuit Model The arrival time at a gate output is determined: either by the earliest controlling input. AND 1313 0202 0606 0303 (assuming a delay bound of 1)

19. Circuit Model The arrival time at a gate output is determined: either by the earliest controlling input; AND 1313 1212 1616 or by the latest non-controlling input. 1717 (assuming a delay bound of 1)

20. Timing Analysis Characterize arrival times symbolically (with BDDs): : set of input assignments that produce 0 : set of input assignments that produce 1 Implicitly: set of input assignments for which output is

21. Timing Analysis Characterize arrival times symbolically (with BDDs): Time-stamp the characteristic sets: arrival time : set of input assignments that produce 0 : set of input assignments that produce 1

22. Initialization internal signals: x primary inputs:

23. Propagation For a controlling input value v, producing an output value w, If there is a change in the characteristic set of a gate’s fan-in:

24. Propagation For non-controlling input values v 1, v 2, v 3 producing an output value w, If there is a change in the characteristic set of a gate’s fan-in:

25. Propagation If there is a change in the characteristic set of a gate’s fan-in: If changes as a result, update its time-stamp: delay in [ 0, t d ]

26. a b x AND c d x OR AND OR Example time 1time 2time 3time 4time 5time 6 0 0 0 0 0 0 0 0 0 0 0 0

27. Timing Analysis The algorithm terminates since the cardinality of each set increases over time; at most. The circuit is combinational iff the “care” set of input assignments is contained within for each output gate g i. The delay bounds on the arrival times for the output gates give a bound on the circuit delay.

28. Multi-Terminal BDDs For finer-grained timing information, preserve a history of the changes. Reference: Bahar et al., “Timing Analysis using ADDs"

29. Synthesis Select best solution through a branch-and-bound search. N1N1 N2N2 N4N4 N7N7 N3N3 N5N5 N8N8 N6N6 N9N9 See The Synthesis of Cyclic Combinational Circuits, DAC’03. Analysis algorithm is used to validate and rank potential solutions.

30. Implementation: CYCLIFY Program Incorporated synthesis methodology in a general logic synthesis environment (Berkeley SIS package). Trials on wide range of circuits –randomly generated –benchmarks –industrial designs. Conclusion: nearly all circuits of practical interest can be optimized with feedback.

31. Optimization for Area and Delay Area and Delay of Berkeley SIS vs. CYCLIFYsolutions. Berkeley SISCaltech CYCLIFY benchmarkAreaDelayAreaImprovementDelayImprovement p82175191674.57%1521.05% t1343173274.66%1417.65% in3599405931.00%3317.50% in2590345585.42%2914.71% 5xp12102318014.29%224.35% bw280282549.29%2028.57% s510452284441.77%2414.29% s1566365424.24%3113.89% duke2742387163.50%3410.53% s14881016439952.07%3420.93% s149410904610791.01%3915.22% Area: number of NAND2/NOR2 gates. Delay: 1 time unit/gate. application of “script.delay” and mapping

32. Discussion Nearly all circuits can be optimized with cycles. Optimizations are significant. Synthesis strategies targeting area and delay: Analysis through symbolic event propagation: Existing methods can be applied to cyclic circuits. Complexity is comparable for cyclic and acyclic circuits.

33. Future Directions Apply more realistic timing models for analysis. Use more efficient symbolic techniques (e.g., use boolean satisfiability (SAT)-based techniques). Incorporate more sophisticated search heuristics into synthesis.