© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Chapter 11 Basic I/O Interface WK 8.

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Objectives Operation of basic I/O operations Decode 8-, 16, and 32-bit addresses for enabling I/O ports Handshaking for I/O operations Interface and program the 82C55 PPI (programmable parallel interface) Using the 82C55 to connect LCDs, LEDs, keyboards, ADCs, DACs, etc. to the processor Interface and program the 16550 programmable serial interface adapter Interface and program the 8254 programmable interval timer Interface DC and stepper motors to the processor

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e I/O Instructions Two types: - Transfer data between the processor accumulator (AL, AX, EAX) register and I/O device: IN and OUT - Transfer string data between memory and I/O device directly: INS and OUTS (for processors above 8086) IN and OUT: The IN instruction (I/O Read): Inputs data from an external I/O device to the accumulator. The OUT instruction (I/O Write): Copies the contents of the accumulator out to an external I/O device. The accumulator is: - AL (for 8-bit I/O), - AX (for 16-bit I/O), - EAX (for 32-bit I/O).

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e I/O Address As with memory, I/O devices have I/O addresses (addresses for the I/O port) Up to 64K I/O bytes can be addressed The 16-bit port address appears on address bus bits A15-A0 This allows I/O devices at addresses 0000H-FFFFH Two ways to specify an I/O port address: - An 8-bit immediate (fixed) address (specified as a byte in the instruction): e.g. IN AX, p8 ; Reads a word from port p8 0000H-00FFH (can only see the first 256 addresses) - A 16-bit address located in register DX (can be easily varied): e.g. OUT DX, AL; outputs the byte in AL to the port whose address is in DX 0000H-FFFFH (upto 16K addresses). i.e. high port addresses are accessible only through DX addressing 00FF

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e I/O Data widths As with memory, I/O ports are also organized as bytes A port can be 1, 2, or 4 bytes wide (not 8 bytes wide) 00F0H 00F1H 00F2H 00F3H LS byte Port Address p8 Port is 1 byte wide Port is 2 bytes wide Port is 4 bytes wide Low Endian scheme: Low address byte contains low end (LS) part of data

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e INS and OUTS I/O instructions They address I/O port using register DX Transfer string data between port and memory - INS: Moves string data to the Extra Segment; ES:DI - OUTS: Moves data from the Data Segment; DS:SI As with other string instructions, DI and SI can be automatically incremented or decremented depending on the state of the DF (direction flag) bit Data width of transfer specified by using INSB, INSW, and INSD for byte, word, and double word Can be prefixed with REP to repeat the instruction for a number of times stored in CX

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e DX (Note corrections) Width of Transfer Determined by the ‘A’ register used I/O Read Width of Transfer Determined by the Instruction used I/O Write No argument, DX by default

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Isolated vs. Memory Mapped I/O can be either: - Isolated, or - Memory mapped Isolated I/O: uses the dedicated I/O instructions (IN, OUT and INS, OUTS) and has its own address space for I/O ports (0000H-FFFFH)- isolated from the memory address space Memory mapped I/O: uses memory reference instructions and a region of the memory address map. So address space is shared between memory and I/O Both techniques can be used with Intel processors But most Intel-based systems e.g. the PC, use isolated I/O Some other processors do not have dedicated I/O instructions and therefore use only memory-mapped I/O addressing, e.g. the PowerPC microprocessor (Macintosh computers)

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Memory and I/O address Maps for the 8086/8088 a.Isolated I/O Using dedicated I/O instructions e.g. IN, OUT b. Memory-mapped I/O Using ordinary memory transfer instructions e.g. MOVE 64 K I/O bytes I/O Port specified in DX, either explicitly or implicitly Port specified immediately as a byte in the I/O instruction 00FF Range of memory addresses assigned for I/O transfers

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e The PC I/O space The PC I/O space mainly exists at locations below I/O port 0400H Main board devices appear at addresses 0000H through 00FFH Early ancillary I/O devices appear at I/O locations 0100H through 03FFH Modern components appear at I/O locations above 0400H The slide on the next page shows many of the I/O devices found in the personal computer

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e 00FF 03FF 0000 Reserved for use by system components and ISA bus The PC I/O Address Space Can Use either: - Fixed (immediate) 8-bit I/O address in instruction, p8 - Variable 16-bit I/O address in register DX 0000 0100 Must use 16-bit variable I/O address in register DX Processor communicates with and controls these peripherals through writing into/reading from their control registers accessed as I/O locations

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e IN (I/O Read) The IN instruction primarily takes he following forms: IN AL,23H;immediate IN AL,DX;DX holds address IN AX,44H IN AX,DX IN EAX,2AH IN EAX,DX Size of data transferred in each case? Data from the I/O port addressed is put on the data bus for the processor to read into the A register

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e OUT (I/O Write) The OUT instruction primarily takes the following forms: OUT 23H,AL;immediate OUT DX,AL;DX holds port OUT 4CH,AX OUT DX,AX OUT 1EH,EAX OUT DX,EAX Size of data transferred in each case? Data from the A register is put on the data bus for latching into the I/O port addressed

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e In embedded systems, most I/O is 8-bits To write the data 00H into I/O port 62H MOV AL,00H OUT 62H,AL or MOV AL,00H MOV DX,62H OUT DX,AL To read a byte from I/O port address 71H: IN AL,71H or MOV DX,71H IN AL,DX

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Basic Input Port (for I/O Reads) The basic input port connects an external set of bits to the microprocessor data bus whenever the microprocessor executes the correct IN instruction with the correct I/O port address Must include a 3-state (Tri-State) buffer to limit access to the processor data bus to the duration of executing the I/O instruction only

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e To  P Pull-up Resistors 0 1 Toggle switches Outputs: Normally Hi-Z Unless device is Selected (both G1 and G2 low) The SEL signal is generated (active low) By decoding: - The address for the I/O port - The I/O READ operation Circuit can be expanded for 16-bit (word) or 32-bit (DWord) interfaces Basic 8-bit Input Interface: Reads the status of 8 toggle switches 3-state buffer

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Basic Output Port (for I/O Writes) The basic output port writes data from the microprocessor data bus to an output port whenever the microprocessor executes the correct OUT instruction with the correct I/O port address Must latch the processor data put on the bus to make it available indefinitely for the port No need for 3-state (Tri-State) buffers as the data bus is at the input side of the latch

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Basic 8-bit Output Interface: Controls 8 LEDs (1: OFF, 0: ON) From  P Data is latched and remains here until the next OUT instruction to this port is executed Circuit can be expanded for 16-bit (word) or 32-bit (DWord) interfaces The SEL is generated (for + ive edge triggering) by decoding: - The address for the I/O port - The I/O WRITE operation Edge-triggered latch

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Parallel Port The parallel port is an example of interfacing slow devices, e.g. a printer, to the processor A printer can print say 100’s of characters per sec (CPS), but the processor can output possibly 1000’s of CPS To achieve ‘flow control’ and proper operation we use a technique called handshaking Handshaking regulates flow of data from the processor to a slower peripheral device to ensure correct operation

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e - Computer (parallel port) has a 25-pin DB25 connector - Printer has a 36-pin Centronics connector Printer side Computer side 8-bit Character data Computer Printer (STB) Computer Printer Strobe Data Into Printer Computer polls ‘Busy’ to see if it can send next character Data

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e ;An assembly language procedure that prints the ASCII contents of BL. PRINTPROCNEAR.REPEAT;Poll the busy line until it goes low IN AL,BUSY;READ the port having the BUSY input TEST AL,BUSY_BIT;test if the Busy bit in the data read is 0 yet ;BUSY_BIT is a mask defining the position ; of the BUSY bit in the port.UNTIL ZERO;End waiting loop if the ZERO flag is set MOV AL,BL;Yes!...move character data to AL OUT PRINTER,AL;and output it to printer- ;PRINTER is address of the printer port ;This also generates the #STB pulse RET PRINTENDP For example, if Busy goes on bit 4 of the BUSY port, BUSY_BIT will be: 00001000 and the instruction TEST AL, BUSY_BIT will AND AL with the bit pattern 00001000. The result will be 0 only if the BUSY Input is 0, setting the ZERO flag and ending the waiting (handshake Loop) BUSY = 0! So output data to Printer! Loop repeatedly reads BUSY & checks if it is low

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Interfacing When connecting external input and output devices to the processor, we must take into account the DC characteristics and drive capabilities of the  P pins, see Chapter 9  P Output PP  P Input Input Devices, e.g. Switches Output Devices, e.g. LEDs Sink Source

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e The most basic input device Switches are passive- do not produce a voltage, often present a logic 0 to a circuit. To make a switch TTL compatible, a pullup resistor is used as shown. The value should be between 1K and 27K. Switches bounce… and this is often undesirable. Input Devices: The Switch TTL Input to  P The pullup resistor does the conditioning required to allow the switch to produce a TTL compatible input to the processor Here, processor reads the switch effect directly- hence bouncing is a problem, especially if input Is used as a clock (Single Pole Single Throw)

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Switch contacts bounce mechanically at the new position With the simple arrangement shown, bounces can lead to the wrong input being read by the processor The effect of switch bounces can be removed either by software, discussed later, or by hardware Hardware solutions add to circuit cost The switch Bouncing Problem TTL Input to  P

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Switch De-bouncing Circuits To Processor - Simpler, cheaper circuit - No pullup resistors required To Processor Processor now senses the output of a bistable flip flop (FF) (with memory) controlled by the switch (not the switch directly as before) Only an instantaneous change in the switch position causes a permanent change in the FF output to the processor A little bounce from the new position will not cause the FF to change state as it remembers (through the feedback) the latest output before the bounce 1111 = No Change from Previous state

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e LED diodes are used in many systems as indicators and as sources of infrared beams LEDs must be forward biased to conduct and emit light When conducting, a typical (Red, Green, or Yellow) LED passes a current of 10 mA with a voltage drop V diode  1.65 V (1.5 V-2 V in practice) A Blue, White, or UltraBright LED passes more current at a larger voltage drop, e.g. 30 mA @ 2.5 V. Output Devices: The LED + _ 1.65 V 10 mA A bit of electronics!

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e 10 mA currents can be easily sunk by a TTL output at the low state (0) (A standard 74 TTL O/P sinks up to 16 mA – lower values for lower power series e.g. 74LS sinks only 4 mA) V out, low  0.1 V V diode  1.65 V To ensure I = 10 mA, R should be Interfacing the LED directly to a TTL O/P R V diode V out I min = 10 mA = +5V Nearest standard resistor value + _

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e If diode takes current > TTL sink current at the low state: Use a transistor to connect the LED Transistor current gain (  = Ic/Ib  100) reduces current requirement from the TTL circuit (e.g. the  P or buffer IC) Ib = Ic/100 = 10mA/100  0.1 mA Rc calculated as before, similar value Rb should not be larger than: Interfacing the LED through a transistor b = Base e = Emitter c = Collector Nearest standard resistor value 0.7V 0.1V 1.65 V + _ Ic = 10 mA Ib = 0.1 mA (TTL) Rb b c e Transistor: Use minimum gain value specified (worst case condition)

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Driving larger currents and voltages; e.g. DC motors, mechanical relays, etc. Large current loads such as motors or large relays require a Darlington pair in place of the transistor driver Two transistor gains in cascade, (  =  ), so smaller base currents from TTL for large load currents Can use 12 V or higher supply Select a transistor that meets both the voltage and current requirements for the load The diode is used to prevent the transistor from being destroyed by the inductive kickback current that appears when the field collapses suddenly in the coil Current can not change instantly through an inductor. If it suddenly drops from I1 to 0, a negative current - I1 is generated which gradually decays to 0. The diode provides a safe path for this current away from the transistor Rb Ic = 1 A 1A/(7000)=0.143 mA (TTL) Diode off In normal operation  0.7V WK 9

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Port Address Decoders As with memory addresses, port addresses must also be decoded to select an I/O device for a particular port number. Memory mapped I/O is identical to memory access decoding (with IO/#IM = 0) Will consider here only isolated I/O (using dedicated instructions: IN, OUT, etc.) Most embedded systems use only fixed I/O addressing: - i.e. Only the least significant eight address bits A7-A0 are decoded. Limits number of I/O ports to 256 (enough) PC systems used fixed/variable I/O addressing: - All 16-bits of the I/O address A15-A0 are decoded, allowing the use of up to 64K ports Decoding is simpler than for memory- smaller # of address lines Isolated I/O transfers are activated using (depending on processor and mode): - IO/#M = 1, M/#IO = 0, #IORC, #IOWC, #RD, #WR, W/#R

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e XXX10111XXX10111 3-to-8 Decoder XXX01111XXX01111 Decoder I/Ps Decoder O/Ps LS part (Select port on decoder) MS part (Enable decoder) A7 …....A0 Address from  P 11110 000 = F0 1st 11110 001 = F1 2 nd ……………………. 11110 111 = F7 7th To ‘Enable’ Inputs on the 8 I/O ports Address Decoding for 8 I/O Ports: F0 to F7 for the 8088 using 8-bit I/O address a. Using a Decoder IC Note: #IO/M decoding is missing!

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e library ieee; use ieee.std_logic_1164.all; entity DECODER_11_11 is port ( A7, A6, A5, A4, A3, A2, A1, A0: in STD_LOGIC; D0, D1, D2, D3, D4, D5, D6, D7: out STD_LOGIC ); end; architecture V1 of DECODER_11_11 is begin D0 <= not( A7 and A6 and A5 and A4 and not A3 and not A2 and not A1 and not A0 ); D1 <= not( A7 and A6 and A5 and A4 and not A3 and not A2 and not A1 and A0 ); D2 <= not( A7 and A6 and A5 and A4 and not A3 and not A2 and A1 and not A0 ); D3 <= not( A7 and A6 and A5 and A4 and not A3 and not A2 and A1 and A0 ); D4 <= not( A7 and A6 and A5 and A4 and not A3 and A2 and not A1 and not A0 ); D5 <= not( A7 and A6 and A5 and A4 and not A3 and A2 and not A1 and A0 ); D6 <= not( A7 and A6 and A5 and A4 and not A3 and A2 and A1 and not A0 ); D7 <= not( A7 and A6 and A5 and A4 and not A3 and A2 and A1 and A0 ); end V1; A7 …....A0 11110 000 = F0 1st 11110 001 = F1 2 nd ……………………. 11110 111 = F7 7th Outputs are active low b. Using a PLD I/O control not decoded

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e library ieee; use ieee.std_logic_1164.all; entity DECODER_11_12 is port ( Z, A12, A10, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0: in STD_LOGIC; D0, D1, D2, D3, D4, D5, D6, D7: out STD_LOGIC ); end; architecture V1 of DECODER_11_12 is begin D0 <= not ( not Z and not A12 and A10 and A9 and A8 and A7 and A6 and A5 and A4 and A3 and not A2 and not A1 and not A0 ); D1 <= not ( not Z and not A12 and A10 and A9 and A8 and A7 and A6 and A5 and A4 and A3 and not A2 and not A1 and A0 ); D2 <= not ( not Z and not A12 and A10 and A9 and A8 and A7 and A6 and A5 and A4 and A3 and not A2 and A1 and not A0 ); D3 <= not ( not Z and not A12 and A10 and A9 and A8 and A7 and A6 and A5 and A4 and A3 and not A2 and A1 and A0 ); D4 <= not ( not Z and not A12 and A10 and A9 and A8 and A7 and A6 and A5 and A4 and A3 and A2 and not A1 and not A0 ); D5 <= not ( not Z and not A12 and A10 and A9 and A8 and A7 and A6 and A5 and A4 and A3 and A2 and not A1 and A0 ); D6 <= not ( not Z and not A12 and A10 and A9 and A8 and A7 and A6 and A5 and A4 and A3 and A2 and A1 and not A0 ); D7 <= not ( not Z and not A12 and A10 and A9 and A8 and A7 and A6 and A5 and A4 and A3 and A2 and A1 and A0 ); end V1; Address Decoding for 8 I/O Ports: for the 8088 with 16-bit I/O address Z = not (A15 & A14 & A13 & A11) I/P 16 I/Ps #(1110111111111011) = #EFFBH Check: Note: I/O control not decoded

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e 16-bit Wide I/O: 8086,286, 386SX Same with memory banks, we have multiple I/O byte banks (each 1 byte) For processors with a 16-bit data bus: 2 banks (for low and high bytes) 64K 8-byte I/O ports  32K 16-bit ports (decoded using most significant 15 bits of the 16-bit I/O address) Which byte in the port is determined by the LSB (A0) and the #BHE: For I/O writes, as with memory, use separate strobe signals (e.g. #BLE or #BHE) for the separate byte ports For reads, normally no action is required as processor reads the byte it wants. This is OK assuming the port responds correctly to the read command from the processor 16-bit (Word) port: Port # starts with A1 not A0 (15 lines  2 15 = 32K 16-bit ports) A0 goes through 1 and 0  it is a don’t care MS byte port LS byte port 32K Word Ports 64K Byte Ports

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Low Byte Port High Byte Port 16-bit Output Port which allows the processor to write into either or both its two separate bytes 40H = 0100 0000 (mostly zeros  use OR function) D0 = A7+#A6+A5+A4+A3+A2+A1+A0+ #IOWC 41H = 0100 0001 D1 = A7+#A6+A5+A4+A3+A2+A1+ #BHE + #IOWC D8 A7 Strobe  P Data In Start with A1 Strobe  P Data In  P Data Bus Output always enabled: Tri-state feature is not utilized Not necessary for output ports Start with A1 This part Is the same For both byte ports I/O Write Width Determine by Narrowest Signal Which is?

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e library ieee; use ieee.std_logic_1164.all; entity DECODER_11_14 is port ( BHE, IOWC, A7, A6, A5, A4, A3, A2, A1, A0: in STD_LOGIC; D0, D1: out STD_LOGIC ); end; architecture V1 of DECODER_11_14 is begin D0 <= A7 or not A6 or A5 or A4 or A3 or A2 or A1 or IOWC or A0; D1 <= A7 or not A6 or A5 or A4 or A3 or A2 or A1 or IOWC or BHE; end V1;

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e 16-bit Input Port: No use of BHE or A0 (Processor knows which byte it wants) Common Strobe for both byte ports No byte selection for READs  P Data Bus Buffers must be Tri-State Because their outputs connect to the Processor data bus! No A0 or BHE 7-bit address Strobe External Data In Dropped A0 7-bit address lines 2 7 = 128 x 2-byte ports (= 256 byte ports) I/O Read

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e library ieee; use ieee.std_logic_1164.all; entity DECODER_11_15 is port ( IORC, A7, A6, A5, A4, A3, A2, A1: in STD_LOGIC; D0: out STD_LOGIC ); end; architecture V1 of DECODER_11_15 is begin D0 <= IORC or A7 or not A6 or not A5 or A4 or A3 or not A2 or A1; end V1; 0 1 1 001 0 A0 0 Lower Byte: 64H Higher byte: 65H 1 The lowest 8-bit address (64H) is used by the software to address this 2-byte port for all READs from its two bytes

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e 32-bit Wide I/O, e.g. for 80486 The only difference between 16-bit wide I/O and 32-bit wide I/O is that 32-bit wide I/O consists of 4 side-by- side 8-bit ports instead of 2. Same as with memory interface: for each doubling of the number of byte ports connected to the data bus  drop one more of the LS address bits So with 80486 we (32-bit data bus) we drop A0 and A1 Next slide illustrates a 32-bit wide input port that decodes only 6 bits of address.

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Common strobe 6-bit address lines, allowing access to 2 6 = 64 x 4-byte ports (= 256 byte ports) Dropped A0, A1 32-bit Wide I/O, e.g. for 80486 XX001110XX001110 Input Port (Read): No bank selection  P Data Bus

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e library ieee; use ieee.std_logic_1164.all; entity DECODER_11_16 is port ( IORC, A7, A6, A5, A4, A3, A2: in STD_LOGIC; D0: out STD_LOGIC ); end; architecture V1 of DECODER_11_16 is begin D0 <= IORC or A7 or not A6 or not A5 or not A4 or A3 or A2; end V1; A1 A0 0 0 1 1 0 1 Determine the 4 addresses of the four byte ports and Verify you get addresses given on the previous slide The lowest 8-bit address (70H) is used by the software to address this 4-byte port (not decoded)

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e I/O for the Pentium Although the Pentium has a 64-bit data bus, only memory transfers use it I/O instructions support a maximum of 32 bit transfers, i.e. over a max of 4-byte ports Pentium has 8 byte enable signals BE0, …, BE7 to allow selecting the byte to be written into a memory bank For I/O, we will use them to select which I/O byte bank to write into for output ports Which bank to read from an input ports is left to the processor (no hardware bank selection for READS) The bank number is determined by the LS 3 bits of the address (replaced by the 8 BEi signals) Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 Bank 0 XX000 XX001 XX010 XX011 XX100 XX101 XX110 XX111 Pentium 8 byte banks. I/O uses a max of 4 banks at a time

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e I/O for the Pentium Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 Bank 0 XX000 XX001 XX010 XX011 XX100 XX101 XX110 XX111 Any bank can be a byte port Four valid 16-bit ports: Moving within the port changes only the LSB of the address Invalid 16-bit port Two valid 32-bit ports: Moving within the port changes only the 2 LSBs of the address Invalid 32-bit port Examples: - Byte port 0034H: 00110100  Bank 4 (i.e. Use BE4) -2-Byte port 005AH-005BH: 01011010-01011011  2,3 (Use BE2, BE3) - 4-byte port 0104H-0107H: ….0100-….0111  4,5,6,7 (Use BE4,BE5,BE6,BE7) Still 16-bit address for I/O

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e 2-byte Output (Write) port for the Pentium at addresses 2000H and 2001H: ….0000-….0001  Banks 0,1 (i.e. use BE0, BE1) A2-A0 Dropped A2-A0 Bank 0 (BE0) Bank 1 (BE1) Outside World  P Data Bus Determine which BEs to use from LS 3-bits of address

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e library ieee; use ieee.std_logic_1164.all; entity DECODER_11_17 is port ( MIO, BE0, BE1, WR, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3: in STD_LOGIC; D0, D1: out STD_LOGIC ); end; architecture V1 of DECODER_11_17 is begin D0 <= MIO or BE0 or not WR or A15 or A14 or not A13 or A12 or A11 or A10 or A9 or A8 or A7 or A6 or A5 or A4 or A3; D1 <= MIO or BE1 or not WR or A15 or A14 or not A13 or A12 or A11 or A10 or A9 or A8 or A7 or A6 or A5 or A4 or A3; end V1; ?

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e The 8255 allows the microprocessor to communicate with the outside world through three programmable 8-bit wide I/O ports The PC uses a few 82C55 (in the chip set) to control the keyboard, speaker, and parallel port The 8255 PPI is available in DIP or surface mount forms Also implemented as functions within modern interface chip sets The 82C55 PPI PPI = Programmable Peripheral Interface

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e A B C 3 programmable 8-bit I/O ports: A, B, C Port A + Upper half of C = Group A (12 bits) Port B + lower half of C = Group B (12 bits) 82C55 DIP Version Data Bus 2-bit Address I/P (select port or Command register for Read or Write) CS Input (low) Read/Write Control On the PC: Two 82C55s -One 82C55 occupies 4 I/O ports 60H-63H: Handling Keyboard, timer, speaker, etc. -One 82C55 occupies 4 I/O ports 378H-37BH Parallel printer port RESET initializes the PPI to operate in mode 0 & all 3 ports as inputs at power up. With all ports as input ports, this avoid damage to the device at Power up 2 Groups 12-bit groups A, B Similar to a 4-byte RAM

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e I/O Port Assignments Group A is Port A and upper ½ of Port C (PC7-PC4). Group B is Port B and lower ½ of Port C (PC3- PC0). A1A0Function 00Port A 01Port B 10Port C 11Command Register Writing into this register Programs the various ports to operate in The various modes and to be used as either inputs or outputs

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e 100100 100100 001 80386SX Processor A7 A6 A5 A4 A3 A2 A1 A0 11 0 0 0 0 0 0 = C0H Port A 11 0 0 0 0 1 0 = C2H Port B 11 0 0 0 1 0 0 = C4H Port C 11 0 0 0 1 1 0 = C6H Comnd Register A1 A0 Inputs on 82C55 Address from 80386SX microprocessor Address from microprocessor Select PPI At decoded  P address

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Programming the 82C55 Using one internal register If bit 7 = 1 select format for Command Byte A If bit 7 = 0 select format for Command Byte B Command Byte A: Programs Groups A and B (as defined in terms of ports A, B, C - previous slide): - as either inputs or outputs - in either modes 0, 1, or 2 Command Byte B: Sets (to 1) or Clears (to 0) the specified one of 8 bits of port C (in modes 1 and 2) Only for mode 0

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e 8255 Modes Mode 0 (for groups A & B)- the most commonly used mode: All 12 bits of the group are simple inputs or simple latched outputs Mode 1 (for groups A & B)- is used occasionally to provide handshaking to an I/O device and operate asynchronously with the device. Most Port C bits provide handshake functions for the operation. A few are controlled separately using the Command byte B format for handshaking I/O. Mode 2 (for group A only- Group B not used)- is a bidirectional mode for Port A only (Port B is not used). Port C provides handshaking signals. Data Control, e.g. Busy, Strobe, etc.

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Programming the 82C55 To program the command register of the 82C55 and select operation use command byte A For example, to program all the ports as outputs and in mode 0 (the most common mode) use: MOV AL,80H MOV DX,COMMAND_PORT OUT DX,AL = C6H in slide 50

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e 7-Segement Display Select Segments: Switched Resistors to GND Anode Cathode Select Segments: Switched Resistors to Vcc

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Multiplexed 7-Segement Display Motivation for MUXing: - Reduce the number of segment drivers by a factor of n Common To all Digits Sequentially Turn ON one digit at a time Recommended rate: 100 – 1500 times per sec n = 8 Digits

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e B: O/P Port: Select # Displayed A: O/P Port: Segment data For selected digit B: O/P Port: Select digit Displayed Transistor switch Controlled by Port B bit Vcc 7 Segment data switches Controlled by Port A bits GND PLD for 14-bit I/O address (A15-A2) + IO/#M decoding Address decoding is similar to That of a 4-byte Read/Write memory Multiplex the eight digit displays (only one is ON at a time) 1 turns segment ON 0 turns digit ON Most Significant (MS) Digit...

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e library ieee; use ieee.std_logic_1164.all; entity DECODER_11_21 is port ( IOM, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3, A2: in STD_LOGIC; D0: out STD_LOGIC ); end; architecture V1 of DECODER_11_17 is begin D0 <= not IOM or A15 or A14 or A13 or A12 or A11 or not A10 or not A9 or not A8 or A7 or A6 or A5 or A4 or A3 or A2; end V1; A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 X X 0700 0701 0702 0703 82C55 4 I/O ports: On chip 14-bit address decoding Using PLD PLD Program for Address Decoding

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e ; Program the 82C55 for Port A and Port B being output ports in mode 0 MOV AL, 80H; 80H Data into AL MOV DX, 703H ; Address of Command Port into DX OUT DX, AL; Write 80H into Command Port ; ;An assembly language procedure that multiplexes the 8-digit display. ;This procedure must be called often enough for the display to appear correctly. DISPPROCNEAR USES AX BX DX SI PUSHF MOV BX,8;load counter with # of display digits MOV AH,7FH;load initial digit selection pattern to enable MS digit (01111111) MOV SI,OFFSET MEM-1;address display data starting at MEM MOV DX,701H;address Port B (for Port A decrement DX) ;Sequentially display all 8 digits starting with MS digit.REPEAT MOV AL,AH;send selection pattern to Port B OUT DX,AL DEC DX;Address Port A (for Digit Data) MOV AL,[BX+SI];send digit data to Port A OUT DX,AL CALL DELAY;wait 1.0 ms leaving displayed digit ON ROR AH,1;adjust selection pattern to point to next digit INC DX;Address port B DEC BX;decrement counter for next lower sig. dig..UNTIL BX == 0 POPF RET DISPENDP...... MEM BX MEM+7 MS Digit 8 bytes of Digit Data LS Digit Procedure for 1 ms delay, e.g. a loop of instructions

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e ; Delay Loop DELAY PROC NEAR USES CX MOV CX, XXXX; XXXX determines delay, = Delay required / loop exec time D1: LOOP D1 RET DELAY ENDP Loop execution time is calculated from instruction data and the clock frequency. An 80486 executes “LOOP D1” in 7 clock cycles With a 20 MHz clock, this amounts to 350 ns XXXX = 1ms/350ns Display Flashing Rate: - Assume the DISP Procedure is called continuously - Ignore instruction execution times relative to delay time (e.g. 350 ns << 1 ms)... Digit Displayed 8 7 2 1... 7 2 1 8 1 ms 8 ms... Flashing rate = 1/8 ms = 125 Hz DISP Proc

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Stepper Motor Interface Wk 10 Stepper motor is digital in nature It rotates in a sequence of discrete steps controlled by sequentially energizing a set of coils Step angles vary from 1  to 15  depending on precision required and cost N Pole lies between the two energized coils Rotation Direction: Anti-clock wise Step angle: 90  45  135  225  315  2 coils driven at a time

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Darlington pairs For high load currents Anti-surge diodes 33H or 66H or CCH or 99H POS Current angular Position (in memory) 33H = 00110011 66H = 01100110 CCH = 11001100 99H = 10011001 ROL ROR Anti-Clockwise Clockwise ROL

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e PORTEQU40H ;An assembly language procedure that controls the stepper motor STEPPROCNEAR USES CX AX MOV AL,POS;get position OR CX,CX;set flag bits IF !ZERO?.IF !SIGN?;if no sign.REPEAT ROL AL,1;rotate step left OUT PORT,AL CALL DELAY;wait 1 ms.UNTILCXZ.ELSE AND CX,7FFFH;make CX positive.REPEAT ROR AL,1;rotate step right OUT PORT,AL CALL DELAY ;wait 1 ms for motor to move.UNTILCXZ.ENDIF MOV POS,AL; Save POSN for next step RET STEPENDP If CX = 0 Quit No rotation req. CX has: - Sign of rotation - # of steps e.g. 0000H (0) 8007H (7,R) 0005H (5,L) CX Positive: Rotate Anti-clockwise CX Negative: Rotate Clockwise

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Interfacing a 4x4 Key Matrix Row Inputs Column Outputs With no keys pressed, all row inputs are 1’s due to the pull up resistors connected to Vcc Column outputs are sequentially scanned as 0’s If key (X,Y) is pressed, it connects the scanning 0 from column X output to row Y input. If no other key is pressed on the same column, this allows the pressed key to be identified. X Y 0 Scan columns with a 0 To locate pressed key O/P I/P 0 00 0 4 0’s To check For any Press/Release

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Scan for the next key pressed and locate its column Wait for last key pressed to be Released Wait for next key to be Pressed Scan again after things have settled, and determine coordinates (row, column) of pressed key Software Switch Debounce Software Switch Debounce Use key position determined To get its corresponding Code stored in a lookup table In memory

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e ;assembly language version; ;KEY scans the keyboard and returns the key code in AL. COLSEQU4 ROWSEQU4 PORTAEQU50H PORTBEQU51H KEYPROCNEAR USES CX BX MOV BL,FFH;compute row mask SHL BL,ROWS MOV AL,0 OUT PORTB,AL;place all zeros on Port B.REPEAT;wait for release.REPEAT CALL SCAN.UNTIL ZERO? CALL DELAY10; Release debounce CALL SCAN.UNTIL ZERO?.REPEAT;wait for key.REPEAT CALL SCAN.UNTIL !ZERO?; (not zero, i.e. not = FF) CALL DELAY10; Press debounce CALL SCAN, scan again after things have settled.UNTIL !ZERO? MOV CX,00FEH.WHILE 1;find column MOV AL,CL OUT PORTB,AL CALL SHORTDELAY;Wait till data outputted to PortB have settled! CALL SCAN.BREAK !ZERO?;Key found at this column- Quit WHILE1! ADD CH,COLS;Key not found at this row- move on to next row – add COLS to CH ROL CL,1 ; AL = 11111101 on 2 nd trial.ENDW.WHILE 1;find row from pattern Read into PortA in SCAN SHR AL,1.BREAK.IF !CARRY? ; LSB of AL is shifted into the carry flag by SHR! So we stop on 1 st zero bit INC CH ; for each shift until row is found.ENDW MOV AL,CH ;get key code into AL: AL = CH = X (COLS) + Y = 4 X + Y; X = 0, 1,..,3, Y = 0, 1,.., 3 RET KEYENDP SCANPROCNEAR IN AL,PORTA;read rows OR AL,BL CMP AL,0FFH;test for no keys RET SCANENDP Program the 8255 for: Port A: Input Port B: Output Size in rows, columns can be set, up to 8 x 8 BL = F0, for rows = 4 BL: 11110000 = F0H AL: XXXX1111 (No Keys Pressed) Oring: 11111111 = FF Keep calling SCAN Until FF (no key pressed) i.e. wait for key release Keep calling SCAN Until (Not FF) (a key pressed) i.e. wait for key stroke Determine X,Y of Pressed Key AL = 11111110 1 st Column After SCAN: AL = XXXX1011 (for a key pressed on row 3) Column Row AL from SCAN ASCII? ZERO: No Press !ZERO: Press

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Ports A and/or B used as latching input ports to store data temporarily from external devices before processor is ready to take the data in. Port C provides the control (handshake) bits: - PC4(2): #STB (strobe) Input latches data into the port latch at the + ive going edge - PC5(1): IBF (Input buffer full) Output indicating (to both external device and  P) that port latch has data - PC3(0): INTR (Interrupt Request) If enabled, used to interrupt the processor. High at + ive going edge of #STB and low when data is read by processor - PC4(2) INTE (Interrupt Enable) Internal bit programmed through PC4(2) for enabling/disabling interrupt generation - PC6,7 General Purpose I/O bits Mode 1: Port A/B for Strobed Input Data from External Device Two ways to interface to the processor: 1.Polled: Processor polls IBF waiting for data to be available in port latch (IBF=1) 2.Interrupt-driven: INTR is used to interrupt the processor when data becomes available in port - saves processor time as Input Automatically the associated C half assumes these functions- no longer separately Programmable (except PC6,7) To  P (Normal) Program with Command Byte B format Port Latch External Bus Data Byte Handshake  P Data Bus For Input Operations…What starts first? External Device Side Microprocessor Side Data strobed in from external device into port latch Data read by microprocessor from port latch Hardware Polling by External Device Software Polling by Processor

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e ;A procedure that reads the keyboard encoder and ;returns the ASCII key code in AL BIT5EQU20H;00100000 Mask defining PC5 (IBF for Port A) PORTCEQU22H PORTAEQU20H READPROCNEAR.REPEAT;poll IBF bit IN AL,PORTC TEST AL,BIT5.UNTIL !ZERO?; Quit polling when bit 5 read is not ZERO (IBF=1) IN AL, PORTA; get ASCII value of key pressed from keyboard RET READENDP Interfacing a Keyboard to  P using Port A in Mode 1 (Strobed Input) 1  s Port A Port C To Processor Data Control (PC5 IBF bit) 8255 should be programmed for operation in: - Mode 1 - With Port A as input Handshake (Polling) Method

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Ports A and/or B used as strobed output ports to write data from processor into external devices. Associated half C bits provide handshake signals for the interface. Port C provides control bits: - PC7(1): #OBF (Output Buffer Full) Activated when port has data written into it by the processor. Deactivated to 1 when #ACK is received from external device indicating that data was read. - PC6(2): #ACK (Acknowledge input) from external device requesting data in port to be put on external bus for reading by external device - PC3(0): INTR (Interrupt Request) Used to interrupt the processor when external device receives data (end of #ACK). - PC6(2) INTE (Interrupt Enable) Internal bit programmed through PC4(2) for enabling/disabling interrupt generation - PC4,5 General Purpose I/O bits Mode 1: Port A/B for Strobed Output Automatically the associated C half assumes these functions- no longer separately programmable From  P Data from mP Is strobed into port latch at trailing edge of #WR from  P by  P Again  P can do its part in two ways: 1.Polling #OBF (high) 2.Getting an interrupt with INTR External Bus Port Latch Data Byte Handshake  P Data Bus For output operations…What starts first? External Device Side Microprocessor Side Software Polling by Processor Hardware Polling by External Device For device to take data: - Enable external bus - Provide a strobe pulse

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e ;A procedure that transfers an ASCII character from AH to the printer ;connected to port B BIT1EQU2 ; Bit PC1 = #OBF for port B PORTCEQU62H PORTBEQU61H CMDEQU63H; The 8255 command byte address PRINTPROCNEAR.REPEAT ;Wait for printer ready to receive a new char- Poll #OBF till low IN AL,PORTC TEST AL,BIT1.UNTIL !ZERO?; #OBF =0 No data in output buffer, so can write into it! MOV AL,AH; Write ASCII char data into port latch OUT PORTB,AL MOV AL,8 ;Generate data strobe pulse OUT CMD,AL MOV AL,9 OUT CMD,AL RET PRINTENDP Interfacing a Printer to  P using Port B in Mode 1 (Strobed Output ) Port B Port C Data Control (PC1 #OBF bit) Strobe data Into Printer Ordinary C I/O bit Set and reset To generate the #DS pulse (Strobe output) signal to Ex Dev #OBF not used As a strobe to printer 1 0 0 0 1 0 0 1 In port C Reset PC4 Set PC4 Data from  P to port latch Data from port latch to Printer

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Mode 2: Port A only for Bidirectional I/O Ports A (only) is used for bidirectional I/O. 5 Port C bits provide bidirectional handshake signals. 3 Port C bits are programmable I/O with Command byte B format. Application: Computer-to-computer comm., GPIB bus Handshake signals combine input handshake and output handshake of mode 1: - For Input: #STB, IBF - For Output: #OBF, #ACK - Common: INTR (qualified by 2 internal enable bits INTE1 and INTE2) Program operates the port bidirectional bus using the OUT and IN instructions I/P Control O/P Control To/From  P

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Mode 2 Example: Processor Sends Data to External Device on the Bidirectional Bus To send Data from processor to external device: 1. Processor checks if #OBF = 1 (No data pending in port) 2. Processor OUTs data to port (Writes it into Port A latch- not on external bus yet) 3. Port lowers #OBF O/P to alert device to take data 4. External device detects 3 and lowers #ACK input to port 5. This raises #OBF high 6. #ACK enables Port external bus to carry latch data so it can be taken by device 7. After device takes data it raises #ACK high I/P Control O/P Control From  P I Ack you have data for me. Please put it on the bus so I can take it! By external device (May need a strobe pulse from  P) By Microprocessor Data in Port A latch, but not on its I/O bus yet Port I/O bus is normally HiZ Enable I/O Bus to carry latch data 1 2 3 4 6 5 7 ;A procedure transmits AH through the bidirectional bus BIT7 EQU 80H PORTC EQU 62H PORTA EQU 60H TRANSPROC NEAR.REPEAT IN AL,PORTC TEST AL,BIT7.UNTIL !ZERO? MOV AL,AH OUT PORTA,AL RET TRANSENDP Wait for #OBF =1 Result = 1 (Not zero)

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Mode 2 Example: Processor Receives Data from External Device on the Bidirectional Bus To Receive Data: 1. External device sending data checks if #IBF = 0 (No pending data in port latch not read by processor) (Hardware Polling) 2. Then it puts its data on external bus and strobes it into port latch using #STB 3. IBF goes high until data is read by processor 4. Processor polls IBF for IBF = 1 to make sure data is in port latch (software polling) 5. Processor reads data from port 6. This automatically lowers IBF to enable further writes I/P Control O/P Control By device on the other side HiZ external bus! (It is OK… processor reads the data bus) To  P By Microprocessor latch Port I/O bus is normally HiZ Hardware Polling for IBF = 0 by remote Device to generate #STB To avoid overwriting existing data in Port not read by processor yet ;A procedure that reads data from the bidirectional bus into AL BIT5 EQU 20H PORTC EQU 62H PORTA EQU 60H READ PROC NEAR.REPEAT ;Wait for IBF = 1 IN AL,PORTC TEST AL,BIT5.UNTIL !ZERO? IN AL,PORTA RET READ PROC NEAR 1 2 3 4 5 Step 4 6 2 Step 5

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Programmable Counter/Interval Timer: 8254 3 Identical and separate 16-bit presentable counters Clock frequency up to 10 MHz  Binary or BCD counting Each can be programmed to operate in any of 6 modes Each can be preset and read under program control Programming by writing into a command register (A1A0=11) Appears as 4 I/O bytes in the processor I/O space (similar to the PPI 82C55) Note similarity with the 82C55: 3 programmable units + 1 Command register Data bus Chip Select (Obtain by Decoding Remaining I/O Address lines) 2-bit address RD/WR Control PIT For each counter: - Clock Input: - ive edge - Gate Input: Function depends on mode, e.g. 1: Count, 0: No count - Output: Changes state on terminal count WK 11

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e The PIT in the PC The timer appears in the PC at I/O ports 20H and 23H inside of the chipset. It controls the speaker and generates a periodic signal at the correct repetition frequency to refresh the dynamic RAM A1A0Function 00Counter 0 01Counter 1 10Counter 2 11Control word (command byte)

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e General Applications Generation of accurate time delays under software control Real Time Clock Event Counter: Interrupt processor when a preset number of events occur Digital one-shot (A pulse of a programmable width generated in response to an event) Programmable frequency clock (fout = fin/n, n determined by software) Square wave generator Complex waveform generation (with a digital to analog converter- DAC) Complex motor control

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Close up of one Counter 2-byte Count Register (Input Latches for writing Initial Counts from  P Into counter) 16-bit Counting Element 2-byte Output Latches for reading counter Parallel output (Read at the counter’s I/O address with the format specified when the counter was programmed) Normally follow counter count and can be read at any time. A “Counter Latch Command” latches the present counter count into them. Will be frozen till read by processor Program the counters By writing into this Control byte (A1A0 = 11) LS MS CR and OL are written/read one byte at a time across the 8-bit data bus Counter Status: Use the Read-back Command to latch into Status Latch for reading by Processor

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Programming the Counters: Write Operations Each counter must be programmed before it can be used A counter is programmed by writing a control word into the control word register (A1A0=11) followed by an initial count into the I/O address of that counter (specified also in the control word) Counting Method: BCD or Binary Counter Mode Reading/Writing Specify Counter to be programmed Initial counts are written into the I/O address of the counter specified, e.g. A1A0 = 01 for counter 1 Initial count bytes or words specified for a counter in a control word should be sent after the control word- but not necessarily immediately following it, and programming of the 3 counters can be interleaved Counter Latch Command Latches present count of specified Counter to its OL. Remains until latch is read by processor

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Programming the Counters: Write Operations All sequences below for the Control Word followed by Initial Count bytes are valid The arrow shows an invalid Sequence. Why?

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e READ Operations: Reading a counter while it is counting Three Ways 1.Simple READ: - Inhibit clocking by G = 0 (Disrupts future count!) to ensure reading stable levels - Read the counter at the proper I/O address (e.g. A1A0=10 for counter 2) 2.Issue a “Counter Latch Command” by writing the appropriate byte into the Control Word Register (A1A0 = 11), with RW1 RW0 = 00 and specifying the address of the required counter SC1 SC0. When this command is executed, Present count at the counter parallel output is latched into the counter’s output latch (OL) and remains fixed until the latch is read by the processor or the counter is re-programmed. Only then it returns to follow the counter count as before. OL bytes must be read in the format specified when the counter was last programmed The command byte during a “Counter latch command”

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e READ Operations: Reading a counter while it is counting Three Ways, Contd. 3.Read Back Command Written into the control word (A1A0=11) To latch Status and/or Count of any of the three counters (Up to all 3 counters can be specified simultaneously) Format for the Counter Status Register (latched into the Status latch if so specified in the Read-Back Command) Shows how the counter was programmed i.e. Count = 00000H Up to 3 Counters The command byte during a “Read back command”

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Mode 0: Event Counter G input = 1 always to enable counting n: Initial Count Number loaded into counter after programming it by the Control Word OUT goes high at terminal count, (n+1) negative clock edges after n is written into Counter Register by software Initial Count n = 5 Written into Counter’s CR Initial Count n = 5 Loaded into Counter... Counter decrements till Terminal Count = 00000H To Processor INTR OUT rises high at terminal (null) count Applications: Interrupt Processor on: Arrival of a predetermined number of events (1  0 clk transitions) = (n+1) Or elapse of a time interval  t = (n+1) Tclk From the writing of n by software into the counter Count down from n till terminal (null) count

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Gate G in this mode is used as the monostable hardware trigger It allows n to be loaded into counter, which clears OUT to 0. OUT remains low until terminal count Duration of the 0 pulse on OUT = n Tclk If Gate goes high again during the OUT pulse, monostable is retriggered to extend the pulse by another duration Initial Count n = 5 Written into Counter’s CR Initial Count n = 5 Loaded into Counter... Counter decrements till Terminal Count = 00000H Mode 1: Hardware Triggered One-Shot (Monostable Multivbrator) OUT rises high at terminal count (Trigger) Note: In this mode G needs not be kept high for counting to be enabled OUT goes low At n loading

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Gate G = 1 always to enable counting OUT frequency = Clock frequency/n OUT Duty cycle (ON:Total) = (n-1):n Initial Count n = 5 Written into Counter’s CR Initial Count n = 5 Loaded into Counter... Counter decrements till Terminal Count = 00000H Mode 2: Divide-by-n Counter (Programmable Frequency Clock) (Trigger) Note: In this mode G needs not be kept high for counting to be enabled OUT goes low At n loading written Into Counter n = 3 Regular Period (3 pulses = n) 2 1

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Gate G = 1 always to enable counting OUT frequency = Clock frequency/n OUT Duty cycle (ON:Total) = (1:2) for n even  1:2 for n odd Initial Count n = 5 Written into Counter’s CR Initial Count n = 5 Loaded into Counter... Counter decrements till Terminal Count = 00000H Mode 3: Divide-by-n Counter but with a Square Wave Output: (Trigger) Note: In this mode G needs not be kept high for counting to be enabled OUT goes low At n loading written Into Counter (Fixed) Regular Period 4 2 2

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Gate G = 1 always to enable counting OUT gives an active low strobe pulse - Strobe pulse duration: 1 clock interval - Delay from writing initial count into counter (software trigger) = (n+1) Tclk Useful for strobing data generated by processor into external devices, e.g. a printer Note similarity with modes 0 and 4 Mode 4: Software Triggered Strobe Output Pulse: written Into Counter

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Gate G is used as a hardware trigger. Not needed high for counting OUT gives an active low strobe pulse - Pulse duration: 1 clock interval - Delay from writing initial count into counter (software trigger) = (n) Tclk Useful for strobing data generated by processor into external devices, e.g. a printer Note similarity with modes 1 and 4 Mode 5: Hardware Triggered Strobe Output Pulse: written Into Counter

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Summary of G effect In the 5 counter modes Event Counter Hardware triggered One shot Divide by N Counter (Square Wave Output) Software triggered Strobe Hardware triggered Strobe

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e 8254 PIT Programming Example 8 MHz Clock Frequency 100 KHz Square Wave:  Mode 3 (requires G = 1) f Out = f in /n n = 8000/100 = 80d 200 KHz non-square wave:  Mode 2 (requires G = 1) f Out = f in /n n = 8000/200 = 40d G = 1 Permanently for Counter 0 and Counter 1 Addresses: Counter0: 700H Counter1: 702H Counter2: 704H Control Word: 706H (Even addresses) A0 is decoded as 0

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e ;A procedure that programs the 8254 timer to function ;as illustrated in Figure 11-34 TIMEPROCNEAR USES AX DX MOV DX,706H;program counter 0 for mode 3 MOV AL,00110110B ;Initial count is 2 bytes (LS first) OUT DX,AL MOV AL,01110100B ;program counter 1 for mode 2 OUT DX,AL MOV DX,700H ;Load initial count 80d into counter 0 MOV AL,80; LS byte of initial count OUT DX,AL MOV AL,0; Then MS byte of initial count OUT DX,AL MOV DX,702H ;Load initial count 40d into counter 1 MOV AL,40 OUT DX,AL MOV AL,0 OUT DX,AL RET TIMEENDP Control Word Waveform from Counter 0 starts here Waveform from Counter 1 starts here Program

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e 1 0 1 1 0 0 ON OFF ON DC Motor Speed and Direction Control Q 0 #Q 1 Rotation in Opposite Direction Q 1 #Q 0 Rotation in One Direction; e.g. clockwise The Q Output (#Q is the complement): No net motion with duty cycle = 1:2 Net motion in either direction With a duty cycle 1:2 Pulse Width Modulation for Speed Control: We use counter 0 and Counter 1: -Both driven by an 8 MHz clock -Both are divide-by-30,720 counters (Mode 2) (output repetition rate = 8 MHz / 30,720 = 260 Hz (motor spec requires this rate, f, to be 60 Hz < f < 1000 Hz) - Bistable is cleared (Q=0) by the #CLR signal from counter 0 and preset (Q=1) by the #PS signal from counter 1 - Duty cycle is varied by controlling the timing of #PS relative to #CLR (Preset: Q  1) (Set bistable) (Clear: Q  0) Set-Reset Bistable (Reset bistable

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Duty Cycle Control The Q Output (#Q is the complement) duty cycle controls motion: No net motion with duty cycle = 1:2 Net motion in either direction With a duty cycle 1:2 Pulse Width Modulation (Speed Control): Duty Cycle: >1:2 Count < 30,720/2 OUT of Counter 1 (mode 2) OUT of Counter 0 (mode 2) Wait for Counter 1 to reach this count and start Counter 0 This is done only once and the system is left to free-run until a different speed is required Duty Cycle = 1:2 Count = 30,720/2 Duty Cycle: >1:2 Count > 30,720/2 Assume 256 different speed control settings: Represented by byte variable in AH (=128 for no motion (1:2), 0 for maximum speed in one direction (<1:2), 255 for maximum speed in the opposite direction (>1:2) - Increment Count for each speed control setting = 30720/256 = 120

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e ;A procedure that controls the speed and direction of the motor ;in Figure 11-40. ; ;AH determines the speed and direction of the motor where ;AH is between 00H and FFH. CNTREQU706H; PIT Control Word CNT0EQU700H CNT1EQU702H COUNTEQU30720 SPEEDPROCNEAR USES BX DX AX MOV BL,AH;calculate count: AH has speed control byte (0  128  255) MOV AX,120 MUL BL; Multiply AH (speed input) by 120 MOV BX,AX; result in AX, save in BX MOV AX,COUNT SUB AX,BX MOV BX,AX; Subtract from 30720, waiting count is in BX MOV DX,CNTR MOV AL,00110100B; program control word OUT DX,AL; for counter 0: Binary, Mode 2, 2 bytes R/W MOV AL,01110100B; same for counter 1 OUT DX,AL MOV DX,CNT1;program counter 1 MOV AX,COUNT;to generate the clear (#CLR) signal for Q (free-running) OUT DX,AL; LS byte of 30720 first MOV AL,AH OUT DX,AL; then MS byte.REPEAT;wait for counter 1 to reach count in BX IN AL,DX; Read LS byte of counter 1 (goes as AL) XCHG AL,AH; Put it in AH IN AL,DX; Read MS byte of counter 1 (goes as AL) XCHG AL,AH; swap AL and AH to put things back to order.UNTIL BX == AX MOV DX,CNT0;program counter 0 MOV AX,COUNT; to generate a set (#PS) for Q (free-running) after that counting ; delay by Counter 1. Note you also load COUNT as with Counter 1 OUT DX,AL; Actual outputting LS byte then MS byte MOV AL,AH; note AX = BX just now OUT DX,AL RET SPEEDENDP

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e The 16550 UART Universal Asynchronous Receiver Transmitter Baud rates up to 1.5 M bauds (signal elements/s) = Data rate (bps) for binary data Compatible with Intel Processors Includes: - A programmable baud rate generator - 16-byte FIFO buffers at inputs and output to help processor deal with data bursts WK 12

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Asynchronous Serial Data Communication We often send data asynchronously using the format illustrated below Asynchronous data are often sent with one start bit and one stop bit to frame the data, which is usually 8-data bits without parity Usually a byte of data

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e The 16550 UART: Functional Description 40 pin DIP Has totally independent Transmitter (TX) and Receiver (RX) Sections This allows communication in the following modes: - Simplex: Only TX or RX is used (one direction all the time) - Half Duplex: TX then RX (two directions at different times) - Full Duplex: TX and RX simultaneously (two directions at the same time) Can control a modem using six signals, e.g. #DSR (Data Set Ready) input, #DTR (Data Terminal Ready) output…. Here the UART is the data terminal and modem is the dataset.

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e The 16550 UART: Pin Assignments 40 pin DIP 3 Address lines IN from Processor (Table 11-5) Baud rate Clock output Chip Select Inputs Modem Interface: Inputs & Outputs Data bus to Processor Interrupt Processor Master Reset (tie to  P Reset I/P) Serial data INput to RX Serial data OUTput from TX Receiver Clock input Read & Write Control inputs from  P User defined outputs Crystal or External Clock Input TX ready to send. Get data to UART with DMA RX ready with data. Move data from UART with DMA Address Strobe (not needed with Intels

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e A2A1A0Function 000Receiver buffer (read data from RX) and transmitter holding (write data to TX). Also write LS byte of baud rate divisor 001Interrupt enable. Also write MS byte of baud rate divisor 010Interrupt identification (read) and FIFO control Register (write) 011Line control Register (write into the line control register) 100Modem control 101Line status (Read the line status register) 110Modem status 111Scratch The 8 I/O Locations on the UART

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e UARTs in the PC Used to control the COM ports of the PC - UART at I/O address 3F8-3FF: COM Port 0 - UART at I/O address 2F8-2FF: COM Port 2

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Programming the UART Two Stages: Initialization Dialog: - Follows RESET - Two parts: * Program the line control register * Program the baud rate generator Operation Dialog (Actual Communication)

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e 16550 Line Control Register I/O Address: A2 A1 A0 = 011 Data Length = 5 bits Data Length > 5 bits Parity Control See next slide To allow programming The baud rate See Table on next slide A break is a minimum of 2 frames of 0’s

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e STPPEFunction 000No parity 001Odd parity 010No parity 011Even parity 100Undefined 101Send/receive 1 (send 1 in place of the parity bit) 110Undefined 111Send/receive 0 (send 0 in place of the parity bit) The 3 Parity Control Bits in the Line Control Register

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Baud RateDivisor Value 11010,473 3003840 1200920 2400480 4800240 9600120 19,20060 38,40030 57,60020 115,20010 Baud rate is programmed by loading a 16-bit divisor for the crystal oscillator (or external input) frequency into the I/O port addresses:  {A2 A1 A0} = 000: LS Byte of divisor  {A2 A1 A0} = 001: MS Byte of divisor Divisor value is determined by the Oscillator frequency and the baud rate required: Divisor = Oscillator frequency / (16 * Baud rate) Table shows divisor values for various data rates with frequency = 18.432 MHz Programming the Baud rate Generator

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e ;Initialization dialog for Figure 11-45 ;Baud rate 9600, 7 data, odd parity, 1 stop LINEEQU0F3H; A2 A1 A0 = 011 for the Line Control Register LSBEQU0F0H; A2 A1 A0 = 000 for LSB of divisor MSBEQU0F1H; A2 A1 A0 = 001 for MSB of divisor FIFOEQU0F2H; A2 A1 A0 = 010 for the FIFO Control Register INITPROCNEAR MOV AL,10001010B OUT LINE,AL ; Enable Baud rate programming See slide 107 ; program Baud 9600 ; Divisor = 120d (see Table on slide 109) MOV AL,120; LSB of divisor OUT LSB,AL MOV AL,0; MS Byte of divisor OUT MSB,AL MOV AL,00001010B;program 7 data, odd OUT LINE,AL;parity, 1 stop ;(& disable baud rate programming?) MOV AL,00000111B;enable transmitter and receiver OUT FIFO,AL;by writing into the FIFO control Reg. RET INITENDP

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e 16550 FIFO Control Register 1 1 1 I/O Address: A2 A1 A0 = 010 Required to enable actual communication (Operation Dialog)

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e 16550 Line Status Register I/O Address: A2 A1 A0 = 101 Before writing data for transmission, Ensure TX is ready to take it (TH = 1) Before reading data from receiver, ensure RX has data (DR = 1) Error status bits Any being 1 indicates An error Operation Dialog Programming

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e ;A procedure that transmits byte in AH via the 16650 UART LSTATEQU0F5H; The Line status register (LSTAT) (A2 A1 A0 = 101) DATAEQU0F0H; TX/RX Data Register at (A2 A1 A0 = 000) SENDPROCNEAR USES AX.REPEAT ;test the TH bit in to see if TX is available IN AL,LSTAT TEST AL,20H;20H is the mask for the TH bit.UNTIL !ZERO? MOV AL,AH OUT DATA,AL ;send data to TX RET SENDENDP (LSTAT)

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e ;A procedure that receives data from the 16550 UART and ;returns it in AL. LSTATEQU0F5H ; The Line status register (LSTAT) (A2 A1 A0 = 101) DATAEQU0F0H ; TX/RX Data Register at (A2 A1 A0 = 000) REVCPROCNEAR.REPEAT IN AL,LSTAT;test DR bit TEST AL,1.UNTIL !ZERO? TEST AL,0EH;test for any error.IF ZERO?;no error IN AL,DATA;Read RX Data Register into AL.ELSE;any error MOV AL,’?’;Put “?” in AL to indicate error.ENDIF RET RECVENDP

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Chapter 11 Basic I/O Interface WK 8.

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© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Chapter 11 Basic I/O Interface WK 8.

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Presentation on theme: "© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Chapter 11 Basic I/O Interface WK 8."— Presentation transcript:

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