1. ALU

2. ALU: Tasks performed in the control states OperationState addDecode op, op=add/sub/and/or/xor. Alu addAluI rel, rel=lt, eq, gt, le, ge, ne. TestI addAdr. Comp. addB.Taken addJR addSavePC addJALR

3. ALU: Control Signals Signals that control the functionality of the ALU: ALUF[2:0] add (active during states: Decode, AluI, Adr.Comp., B.Taken,SavePC, JR, JALR). test (active during states: TestI). ALUF[2:0] – arithmetic / logical ALU operations 011add 010sub 110and 101or 100xor ALUF[2:0] – test conditions 001gt 010eq 011ge 100lt 101ne 110le IR[2:0] = func[2:0] IR[28:26] = opcode[2:0]

4. MUX(32) OR(32) AND(32) XOR(32) MUX(32) Comparator(32) OR INV MUX(32) MUX(3) ALU: Implementation Next slide

5. ZERO(32) AND INV AND INV OR AND OR ALU: Implementation (cont’) Comparator

6. “Register B” The instructions in which register B is loaded: add sub and or xor store Register B is not involved in computations during instructions in which it need not be loaded. Therefore, functionality is correct. Loading register B always (during Decode state), shortens the length of the path in the Control State Machine when executing instructions that need register B loaded.