1. Dipartimento di Informatica - Università di Verona Networked Embedded Systems The HW/SW/Network Cosimulation-based Design Flow Introduction Transaction Level Modeling (TLM) HW/SW/Network design flow Case study: V-CLIP V-CLIP: refinement steps HW/SW – Network interfaces

2. 2 HW/SW/Network co-design and co-simulation framework Introduction Networked embedded systems represent an important class of digital systems routers, wireless access points, wireless sensor networks, mobile phones, etc. Aspects to be modeled and simulated: Hardware Software Network Different design and modeling tools should be combined

3. 3 TLM Algo (specifications) Refinement RTL Synthesis TL3 TL2 TL1 TLM TLM: Transaction Level Modeling

4. 4 LevelUseFeatures TL3 Executable specifications and first level of functional partitioning of data and control. System proof of concepts.  Implementation architecture-abstract.  Untimed functionalities modeling.  Event-driven simulation semantics.  Point-to-point Initiator-Target connection.  Abstract data types. TL2 Hardware architectural performance and detailed behavior analysis. HW/SW partitioning and co- development. Cycle performance estimation.  Mapping ideal architecture into resource-constrained world.  Memory/Register map accurate.  Bit-width and transfer-size constrained data types to allow mapping to bus bursts or fragments of bursts.  Split pipeline with time delays. TL1 Detailed analysis and low level SW development. Modeling CA interfaces for abstract simulation models of IP blocks such as embedded processors. CA performance simulation.  Clock-accurate protocols mapped to the chosen HW interfaces and bus structure.  Interface pins are hidden.  Byte-accurate data Transactions have internal structure (protocols, data, clock).  Parametrizable to model different bus protocol and signal interfaces. TLM: Transaction Level Modeling

5. 5 TL3 TL2 TL1 RTL TLM refinement TL3 TL2 TL1 RTL Network alternatives TLM/Network refinement HW/SW/Network design flow

6. 6 V-CLIP: Voice over IP client IP network Voice over IP client

7. 7 V-CLIP: mapping to available tools RTP/UDP connection Voice Signal Generator ADPCM Coder RTP Packet Generator SystemC (HW/SW) NS-2 (network) Linux Workstation Voice player

8. 8 V-CLIP: block diagram

9. 9 Step 1 system: V-CLIP TL3 Network (NS2) SOURCE SC-NS interface TL3 SystemC RTP ADPCM Untimed functionality modeling Architecture-abstract implementation Abstract data types High simulation speed! SystemC 2.1 (standard IEEE 1666) Standard OSCI TLM API

10. 10 00023 10Mb/s 64kb/s RTP voice SystemC Actual network ns_sc_agent  Source Linear PCM 16000 sample/s, 16 bit/sample --> 256 kb/s  After ADPCM compression: 64 kb/s  RTP: 1000 byte/packet --> 125ms algorithmic delay Step 1 network

11. 11 000 1 23 10Mb/s 80kb/s generic UDP RTP voice Constant bitrate (CBR) generator SystemC Actual network ns_sc_agent Step 2: activation of concurrent traffic

12. 12 Step 3: hw vs. network parameters setting 00023 10Mb/s 80 kb/s RTP voice SystemC Actual network ns_sc_agent

13. 13 Step 4: V-CLIP TL2 ADPCM (HW) Network (NS2) CPU (SW) Request FIFO Response FIFO SOURCE RTP SC-NS interface TL2 SystemC First HW/SW partitioning High-level bus channel Non-blocking calls put() request and get() response Bus arbiter and decoder Event driven simulation Arbiter Decoder Bus

14. 14 ADPCM (HW) Network (NS2) AMBA AHB Bus CPU (SW) TL2 clk Master transactor Request FIFO Response FIFO SOURCE RTP Master transactor Slave transactor SC-NS interface Slave transactor TL1 TL2 SystemC Arbiter Decoder Clock-accurate simulation Clock-accurate protocols mapped to the chosen HW interfaces and bus structures AMBA Bus Signal level communication with the bus Performance analysis Step 5: V-CLIP TL1

15. 15 Step 6: V-CLIP TL1/RTL Network (NS2) CPU (SW) TL2 Master transactor Request FIFO Response FIFO SOURCE RTP Master transactor Slave transactor SC-NS interface Slave transactor TL2 SystemC adpcm transactor AMBA AHB Bus ADPCM RTL clk TL1 clk ADPCM RTL synthesizable

16. 16 V-CLIP: overall design flow

17. 17 V-CLIP SystemC/VHDL CPU (SW) TL2 Master transactor Request FIFO Response FIFO SOURCE RTP Master transactor Slave transactor sc-ns interface Slave transactor TL2 SystemC adpcm transactor AMBA AHB Bus ADPCM RTL clk TL1 clk VHDL ModelSim© Mentor Graphics SystemC – VHDL co-simulation RTL IP-cores reuse

18. 18 V-CLIP: sc-ns interfaces Network (NS2) CPU (SW) TL2 Master transactor sc_ns_link interface (Ethernet) Slave transactor TL2 SystemC TCP/IP RTP NS node IP packets clk TL1 Network (NS2) CPU (SW) TL2 Master transactor sc_ns_agent interface Slave transactor TL2 SystemC RTP NS agent UDP packets clk TL1