1. A clocked synchronous state-machine changes state only when a triggering edge or “tick” occurs on the clock signal. ReturnNext  “State-machine”: is a generic name given to sequential circuits.  “Clocked”: refers to the fact that their storage elements (flip—flop) employ a clock input.  “Synchronous”: means that all of the flip-flops use the same clock signal.  “Asynchronous”: means that each of the flip- flops use the different clock signal. 7.3 Clocked Synchronous State-Machine Structure

2. Next-state Logic F State Memory clock input Output Logic G inputs clock signal excitation outputs current state NextBackReturn 7.3 Clocked Synchronous State-Machine Structure 7.3.1 State-Machine Structure 1. Mealy machine State-Machine Structure includes two types: Mealy machine and Moore machine.

3. NextBackReturn  Output Equation  Excitation Equation Next state = F (current state, input) W = H (Q n, X ) Output = G (current state, input) Z = G (Q n, X ) Q n +1 = F (Q n, X )  State Equation (Transition Equation) 7.3 Clocked Synchronous State-Machine Structure

4. Next-state Logic F State Memory clock input Output Logic G inputs clock signal excitation outputs current state NextBackReturn 2. Moore machine  Output Equation Output = G (current state) Z = G (Q n ) 7.3 Clocked Synchronous State-Machine Structure

5. The outputs during one clock period depend on the state and inputs during the previous clock period. NextBackReturn 3. Mealy machine with pipelined outputs Next-state Logic F State Memory clock input Output Logic G inputs clock signal excitation pipelined outputs current state Output Pipeline Memory clock input 7.3 Clocked Synchronous State-Machine Structure

6. BackReturn 7.3.2 Characteristic Equations S-R latch Q n+1 = S+R · Q n D latch Q n+1 = D Edge-triggered D flip-flop Q n+1 = D D flip-flop with enable Q n+1 = EN · D+EN · Q n Master /slave S-R flip-flop Q n+1 = S+R · Q n Master /slave J-K flip-flop Q n+1 = J · Q n +K · Q n Edge-triggered J-K flip-flop Q n+1 = J·Q n +K·Q n T flip-flop Q n+1 = Q n T flip-flop with enable Q n+1 = EN · Q n +EN · Q n 7.3 Clocked Synchronous State-Machine Structure