1. CSCI 660 EEGN-CSCI 660 Introduction to VLSI Design Lecture 2 Khurram Kazi Some of the slides were taken from K Gaj ’ s lecture slides from GMU ’ s VHDL course webpage

2. CSCI 660 2 Naming Conventions and Labeling (1)  VHDL is not case sensitive Example: Names or labels databus Databus DataBus DATABUS are all the same

3. CSCI 660 3 Naming and Labeling (2) General rules of thumb (according to VHDL-87) 1.All names should start with an alphabet character (a-z or A-Z) 2.Use only alphabet characters (a-z or A-Z) digits (0-9) and underscore (_) 3.Do not use any punctuation or reserved characters within a name (!, ?,., &, +, -, etc.) 4.Do not use two or more consecutive underscore characters (__) within a name (e.g., Sel__A is invalid) 5.All names and labels in a given entity and architecture must be unique

4. CSCI 660 4 Free Format  VHDL is a “free format” language No formatting conventions, such as spacing or indentation imposed by VHDL compilers. Space and carriage return treated the same way. Example: if (a=b) then or if (a=b)then or if (a = b) then are all equivalent

5. CSCI 660 5 Comments: A must for Code Readability; Use them wisely  Comments in VHDL are indicated with a “double dash”, i.e., “--”  Comment indicator can be placed anywhere in the line  Any text that follows in the same line is treated as a comment  Carriage return terminates a comment  No method for commenting a block extending over a couple of lines Examples: -- main subcircuit Data_in <= Data_bus; -- reading data from the input FIFO

6. CSCI 660 6 Recapping: Entity Declaration  Entity Declaration describes the interface of the component, i.e. input and output ports. ENTITY nand_gate IS PORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC ); END nand_gate; Reserved words Entity name Port names Port type Semicolon No Semicolon Port modes (data flow directions)

7. CSCI 660 7 Mode In a Entity Port signal Driver resides outside the entity

8. CSCI 660 8 Mode out Entity Port signal Driver resides inside the entity Can’t read out within an entity z c <= z c

9. CSCI 660 9 Mode out with signal Port signal Entity Driver resides inside the entity Signal X can be read inside the entity x c z z <= x c <= x

10. CSCI 660 10 Mode inout – Infers bi-directionality: Under most circumstances avoid using this construct Signal can be read inside the entity Entity Port signal Driver may reside both inside and outside of the entity a Use this construct in modeling bi-directional pads.

11. CSCI 660 11 Mode buffer : This construct not synthesis friendly (dependent on specific tools) Entity Port signal Driver resides inside the entity Port signal Z can be read inside the entity c z c <= z

12. CSCI 660 12 Summarizing: Port Modes The Port Mode of the interface describes the direction in which data travels with respect to the c omponent  In : Data comes in this port and can only be read within the entity. It can appear only on the right side of a signal or variable assignment.  Out : The value of an output port can only be updated within the entity. It cannot be read. It can only appear on the left side of a signal assignment.  Inout : The value of a bi-directional port can be read and updated within the entity model. It can appear on both sides of a signal assignment.  Buffer: Used for a signal that is an output from an entity. The value of the signal can be used inside the entity, which means that in an assignment statement the signal can appear on the left and right sides of the <= operator

13. CSCI 660 13 STD_LOGIC Demystified

14. CSCI 660 14 STD_LOGIC What is STD_LOGIC you ask? LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY nand_gate IS PORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC); END nand_gate; ARCHITECTURE model OF nand_gate IS BEGIN z <= a NAND b; END model;

15. CSCI 660 15 STD_LOGIC type demystified Valu e Meaning ‘X’Forcing (Strong driven) Unknown ‘0’Forcing (Strong driven) 0 ‘1’Forcing (Strong driven) 1 ‘Z’High Impedance ‘W’Weak (Weakly driven) Unknown ‘L’ Weak (Weakly driven) 0. Models a pull down. ‘H’ Weak (Weakly driven) 1. Models a pull up. ‘-’Don't Care

16. CSCI 660 16 More on STD_LOGIC Meanings (1) ‘1’ ‘0’ ‘X’ Contention on the bus X

17. CSCI 660 17 More on STD_LOGIC Meanings (2) Output drive buffers in High Impedance state (also known to be in tri-state): Used when multiple drivers on the same wire or bus

18. CSCI 660 18 More on STD_LOGIC Meanings (4) Do not care. Can be assigned to outputs for the case of invalid inputs(may produce significant improvement in resource utilization after synthesis). Use with caution ‘1’ = ‘-’ give FALSE ‘-’

19. CSCI 660 19 Resolving logic levels X 0 1 Z W L H - X X X X X X X X X 0 X 0 X 0 0 0 0 X 1 X X 1 1 1 1 1 X Z X 0 1 Z W L H X W X 0 1 W W W W X L X 0 1 L W L W X H X 0 1 H W W H X - X X X X X X X X

20. CSCI 660 20 Signals: Elaborated SIGNAL a : STD_LOGIC; SIGNAL b : STD_LOGIC_VECTOR(7 DOWNTO 0); wire a bus b 1 8

21. CSCI 660 21 Standard Logic Vectors SIGNAL a: STD_LOGIC; SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL c: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL d: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL e: STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL f: STD_LOGIC_VECTOR(8 DOWNTO 0); ………. a <= ‘1’; b <= ”0000”; -- Binary base assumed by default c <= B”0000”; -- Binary base explicitly specified d <= ”0110_0111”; -- You can use ‘_’ to increase readability e <= X”AF67”; -- Hexadecimal base f <= O”723”; -- Octal base

22. CSCI 660 22 Vectors and Concatenation SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL c, d, e: STD_LOGIC_VECTOR(7 DOWNTO 0); a <= ”0000”; b <= ”1111”; c <= a & b; -- c = ”00001111” d <= ‘0’ & ”0001111”; -- d <= ”00001111” e <= ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘1’ & ‘1’ & ‘1’ & ‘1’; -- e <= ”00001111”

23. CSCI 660 23 VHDL Design Styles

24. CSCI 660 24 VHDL Design Styles Components and interconnects structural VHDL Design Styles dataflow Concurrent statements behavioral Registers State machines Test benches Sequential statements Subset most suitable for synthesis

25. CSCI 660 25 xor3 Example

26. CSCI 660 26 Entity xor3 ENTITY xor3 IS PORT( A : IN STD_LOGIC; B : IN STD_LOGIC; C : IN STD_LOGIC; Result : OUT STD_LOGIC ); end xor3;

27. CSCI 660 27 Dataflow Description  Describes how data moves through the system and the various processing steps.  Data Flow uses series of concurrent statements to realize logic. Concurrent statements are evaluated at the same time; thus, order of these statements doesn’t matter.  Data Flow is most useful style when series of Boolean equations can represent a logic.

28. CSCI 660 28 Dataflow Architecture (xor3 gate) ARCHITECTURE dataflow OF xor3 IS SIGNAL U1_out: STD_LOGIC; BEGIN U1_out <=A XOR B; Result <=U1_out XOR C; END dataflow; U1_out

29. CSCI 660 29 Structural Architecture (xor3 gate) ARCHITECTURE structural OF xor3 IS SIGNAL U1_OUT: STD_LOGIC; COMPONENT xor2 IS PORT ( I1 : IN STD_LOGIC; I2 : IN STD_LOGIC; Y : OUT STD_LOGIC ); END COMPONENT; BEGIN U1: xor2 PORT MAP (I1 => A, I2 => B, Y => U1_OUT); U2: xor2 PORT MAP ( I1 => U1_OUT, I2 => C, Y => Result); END structural; A B C ResultXOR3

30. CSCI 660 30 Component and Instantiation (1)  Named association connectivity (recommended) COMPONENT xor2 IS PORT( I1 : IN STD_LOGIC; I2 : IN STD_LOGIC; Y : OUT STD_LOGIC ); END COMPONENT; U1: xor2 PORT MAP (I1 => A, I2 => B, Y => U1_OUT);

31. CSCI 660 31 COMPONENT xor2 IS PORT( I1 : IN STD_LOGIC; I2 : IN STD_LOGIC; Y : OUT STD_LOGIC ); END COMPONENT; U1: xor2 PORT MAP (A, B, U1_OUT); Component and Instantiation (2)  Positional association connectivity (not recommended)

32. CSCI 660 32 Structural Description  Structural design is the simplest to understand. This style is the closest to schematic capture and utilizes simple building blocks to compose logic functions.  Components are interconnected in a hierarchical manner.  Structural descriptions may connect simple gates or complex, abstract components.  Structural style is useful when expressing a design that is naturally composed of sub-blocks.

33. CSCI 660 33 Behavioral Architecture (xor3 gate) ARCHITECTURE behavioral OF xor3 IS BEGIN xor3_behave: PROCESS (A,B,C) BEGIN IF ((A XOR B XOR C) = '1') THEN Result <= '1'; ELSE Result <= '0'; END IF ; END PROCESS xor3_behave; END behavioral ;

34. CSCI 660 34 Behavioral Description  It accurately models what happens on the inputs and outputs of the black box (no matter what is inside and how it works).  This style uses PROCESS statements in VHDL.

35. CSCI 660 35 Concurrent Statements vs. Sequential Statements  Concurrent statements implies the code is being executed in parallel.  Combinatorial logic is a good example of concurrent behavior  Output of the combinatorial logic is dependent on its inputs: i.e., as soon as the input changes, the output changes.  Sequential statements imply that the output is dependent on previous state  This requires some storage elements connected to combinatorial logic through feedback loop

36. CSCI 660 36 Sequential Code  VHDL Code inside the Processes, Functions and Procedures are executed sequentially.  However, as a whole, any of the blocks of code are executed in parallel

37. CSCI 660 37 Example of Concurrent Code Library ieee; USE ieee.std_logic_1164.all; ENTITY mux IS PORT( a, b, c, d, s0, s1: std_logic; y: out std_logic); END mux; Architecture pure_logic OF mux IS BEGIN y <= (a AND NOT s1 AND NOT s0) OR (b AND NOT s1 and s0) OR (c AND s1 AND NOT s0) OR (d AND s1 AND S0); END pure_logic;

38. CSCI 660 38 Example of Concurrent Code: Using WHEN / ELSE Library ieee; USE ieee.std_logic_1164.all; ENTITY mux IS PORT( a, b, c, d : IN std_logic; sel: IN std_logic_vector (1 downto 0); y: out std_logic); END mux; Architecture mux1 OF mux IS BEGIN y <= a WHEN sel = “00” ELSE b WHEN sel = “01” ELSE c WHEN sel = “10” ELSE d; END mux1;

39. CSCI 660 39 Example of Concurrent Code: Using WITH / SELECT / WHEN Library ieee; USE ieee.std_logic_1164.all; ENTITY mux IS PORT( a, b, c, d : IN std_logic; sel: IN std_logic_vector (1 downto 0); y: out std_logic); END mux; Architecture mux2 OF mux IS BEGIN WITH sel SELECT y <= a WHEN “00”,-- notice “,” instead of “;” b WHEN “01”, c WHEN “10”, d WHEN OTHERS;-- cannot be “d WHEN “11” “ END mux2;

40. CSCI 660 40 BLOCK  There are two kinds of BLOCK statements:  Simple  Guarded

41. CSCI 660 41 BLOCK  Simple  This represents only a way of locally partitioning the code. It allows a set of concurrent statements to be clustered into a BLOCK.  The main intent is to make the code more readable. Label: BLOCK [declarative part] BEGIN (concurrent statements) END BLOCK label;

42. CSCI 660 42 BLOCK: Simple ARCHITECTURE example……… BEGIN block1: BLOCK BEGIN (concurrent statements) END BLOCK block1; block2: BLOCK BEGIN (concurrent statements) END BLOCK block2; ……….. END example;

43. CSCI 660 43 BLOCK: Guarded  Guarded BLOCK is a special kind of BLOCK, which includes an additional expression, called guard expression  A guarded statement in a guarded BLOCK is executed only when the guard expression is TRUE. Label: BLOCK (guard expression) [declarative part] BEGIN (concurrent guarded and unguarded statements) END BLOCK LABEL;

44. CSCI 660 44 BLOCK: Guarded Library ieee; USE ieee.std_logic_1164.all; ENTITY latch IS PORT( d, clk : IN std_logic; q: out std_logic); END latch; Architecture latch OF latch IS BEGIN b1: BLOCK (clk = ‘1’) BEGIN Q <= GUARDED d; END BLOCK b1; END latch; Recommendation: Do not use this construct of Latches or Flip Flops. Use Processes instead!!

45. CSCI 660 45 BLOCK: Guarded Library ieee; USE ieee.std_logic_1164.all; ENTITY dff IS PORT( d, rst, clk : IN std_logic; q: out std_logic); END dff; Architecture latch OF latch IS BEGIN b1: BLOCK (clk’EVENT AND clk = ‘1’) BEGIN Q <= GUARDED ‘0’ WHEN rst = ‘1’ ELSE d; END BLOCK b1; END dff; Recommendation: Do not use this construct of Latches or Flip Flops. Use Processes instead!!

46. CSCI 660 46 Anatomy of a Process [label:] process [(sensitivity list)] [VARIABLE name type [range] [:= initial_value;]] begin (sequential code) end process [label]; OPTIONAL

47. CSCI 660 47 Process: Statement Part Contains Sequential Statements to be Executed Each Time the Process Is Activated Typically a process is activated by any activity on the signals listed in the sensitivity list Condition related to WAIT is fulfilled

48. CSCI 660 48 A process can be given a unique name using an optional LABEL This is followed by the keyword PROCESS The keyword BEGIN is used to indicate the start of the process All statements within the process are executed SEQUENTIALLY. Hence, order of statements is important. A process must end with the keywords END PROCESS. TESTING: process begin TEST_VECTOR<=“00”; wait for 10 ns; TEST_VECTOR<=“01”; wait for 10 ns; TEST_VECTOR<=“10”; wait for 10 ns; TEST_VECTOR<=“11”; wait for 10 ns; end process;  A process is a sequence of instructions referred to as sequential statements. What is a PROCESS? The Keyword PROCESS

49. CSCI 660 49 Behavioral VHDL (subset) sequential signal assignment (  ) if-then-else statement wait until wait for Major instructions Selected sequential statements

50. CSCI 660 50 PROCESS with a SENSITIVITY LIST  List of signals to which the process is sensitive.  Whenever there is an event on any of the signals in the sensitivity list, the process fires.  Every time the process fires, it will run in its entirety.  WAIT statements are NOT ALLOWED in a processes with SENSITIVITY LIST. label: process ( sensitivity list ) declaration part begin statement part end process;

51. CSCI 660 51 Processes in VHDL Processes Describe Sequential Behavior Processes in VHDL Are Very Powerful Statements Allow to define an arbitrary behavior that may be difficult to represent by a real circuit Not every process can be synthesized Use Processes with Caution in the Code to Be Synthesized Use Processes Freely in Testbenches

52. CSCI 660 52 Component Equivalent of a Process All signals which appear on the left of signal assignment statement (<=) are outputs e.g. y, z All signals which appear on the right of signal assignment statement (<=) or in logic expressions are inputs e.g. w, a, b, c All signals which appear in the sensitivity list are inputs e.g. clk Note that not all inputs need to be included in the sensitivity list priority: PROCESS (clk) BEGIN IF w(3) = '1' THEN y <= "11" ; ELSIF w(2) = '1' THEN y <= "10" ; ELSIF w(1) = c THEN y <= a and b; ELSE z <= "00" ; END IF ; END PROCESS ; w a y z priority b c clk

53. CSCI 660 53 Registers

54. CSCI 660 54 ClockD 0 1 1 – 0 1 0 1 Truth table Graphical symbol t 1 t 2 t 3 t 4 Time Clock D Q Timing diagram Q(t+1) Q(t) D latch D Q Clock

55. CSCI 660 55 Clk D   0 1 0 1 Truth table t 1 t 2 t 3 t 4 Time Clock D Q Timing diagram Q(t+1) Q(t) D flip-flop D Q Clock Graphical symbol 0 – Q(t) 1 –

56. CSCI 660 56 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY latch IS PORT ( D, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END latch ; ARCHITECTURE Behavior OF latch IS BEGIN PROCESS ( D, Clock ) BEGIN IF Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior; D latch D Q Clock

57. CSCI 660 57 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Clock: INSTD_LOGIC ; Q: OUTSTD_LOGIC) ; END flipflop ; ARCHITECTURE Behavior_1 OF flipflop IS BEGIN PROCESS ( Clock ) BEGIN IF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior_1 ; D flip-flop D Q Clock

58. CSCI 660 58 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Clock: INSTD_LOGIC ; Q: OUTSTD_LOGIC) ; END flipflop ; ARCHITECTURE Behavior_2 OF flipflop IS BEGIN PROCESS BEGIN WAIT UNTIL Clock'EVENT AND Clock = '1' ; Q <= D ; END PROCESS ; END Behavior_2 ; D flip-flop D Q Clock

59. CSCI 660 59 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ; ARCHITECTURE Behavior OF flipflop IS BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN Q <= '0' ; ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ; D flip-flop with asynchronous reset D Q Clock Resetn

60. CSCI 660 60 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ; ARCHITECTURE Behavior OF flipflop IS BEGIN PROCESS BEGIN WAIT UNTIL Clock'EVENT AND Clock = '1' ; IF Resetn = '0' THEN Q <= '0' ; ELSE Q <= D ; END IF ; END PROCESS ; END Behavior ; D flip-flop with synchronous reset D Q Clock Resetn

61. CSCI 660 61 8-bit register with asynchronous reset LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY reg8 IS PORT ( D: IN STD_LOGIC_VECTOR(7 DOWNTO 0) ; Resetn, Clock: IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ; END reg8 ; ARCHITECTURE Behavior OF reg8 IS BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN Q <= "00000000" ; ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ;` Resetn Clock reg8 88 DQ

62. CSCI 660 62 N-bit register with asynchronous reset LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY regn IS GENERIC ( N : INTEGER := 16 ) ; PORT ( D: IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Resetn, Clock: IN STD_LOGIC ; Q: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END regn ; ARCHITECTURE Behavior OF regn IS BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN Q '0') ; ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ; Resetn Clock regn NN DQ

63. CSCI 660 63 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY regn IS GENERIC ( N : INTEGER := 8 ) ; PORT (D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Enable, Clock: IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END regn ; ARCHITECTURE Behavior OF regn IS BEGIN PROCESS (Clock) BEGIN IF (Clock'EVENT AND Clock = '1' ) THEN IF Enable = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ; N-bit register with enable Q D Enable Clock regn NN

64. CSCI 660 64 Counters

65. CSCI 660 65 LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY upcount IS PORT (Clear, Clock: IN STD_LOGIC ; Q : BUFFER STD_LOGIC_VECTOR(1 DOWNTO 0) ) ; END upcount ; ARCHITECTURE Behavior OF upcount IS BEGIN upcount: PROCESS ( Clock ) BEGIN IF (Clock'EVENT AND Clock = '1') THEN IF Clear = '1' THEN Q <= "00" ; ELSE Q <= Q + “01” ; END IF ; END PROCESS; END Behavior ; 2-bit up-counter with synchronous reset Q Clear Clock upcount 2

66. CSCI 660 66 LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY upcount IS PORT ( Clock, Resetn, Enable : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)) ; END upcount ; 4-bit up-counter with asynchronous reset (1) Q Enable Clock upcount 4 Resetn

67. CSCI 660 67 ARCHITECTURE Behavior OF upcount IS SIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0) ; BEGIN PROCESS ( Clock, Resetn ) BEGIN IF Resetn = '0' THEN Count <= "0000" ; ELSIF (Clock'EVENT AND Clock = '1') THEN IF Enable = '1' THEN Count <= Count + 1 ; END IF ; END PROCESS ; Q <= Count ; END Behavior ; 4-bit up-counter with asynchronous reset (2) Q Enable Clock upcount 4 Resetn