1. iNFAnt: NFA Pattern Matching on GPGPU Devices Author: Niccolo’ Cascarano, Pierluigi Rolando, Fulvio Risso, and Riccardo Sisto Published in: ACM SIGCOMM Computer Communication Review 40(5) 2010 Presenter: Fang-Chen Kuo Date: 2011/11/16

2. Hammer or Ladder ? Hammer: Reduce Overhead  Wide Word Access  Result Cache  Memory Hierarchy Ladder: Cover Overhead  Multi-thread  Asynchronous Memory

3. CUDA Memory used in iNFAnt Shared Memory  Fast (tens clock cycle)  16KB per MP Global Memory  Large, 4GB for C1060  High Bandwidth, High Latency  Cover latency by thread scheduling

4. Wide Word Access Hardware controller tries to automatically coalesce many smaller memory accesses in fewer, larger transactions at run-time. All the addresses must fall within the same naturally-aligned 256-byte memory area.

5. State First or Symbol First ? State first:  Access all transitions for the current state  But there is only one current symbol Symbol first:  Access all transitions for the current symbol  Only one current state ?

6. NFA vs DFA DFA  One active state  Memory Consumption NFA  Many active state  Higher Per-Symbol Traversal cost  Time Consumption  Prefer Hardware

7. Symbol-first representation (Source, Dest) tuple Store in Global Memory 16 bits

8. Traversal Algorithm 1: currentsv initialsv 2: while :input:empty do 3: c input:first 4: input input:tail 5: futuresv currentsv ^ persistentsv 6: while a transition on c is pending do 7: src transition source 8: dst transition destination 9: if currentsv[src] is set then 10: atomicSet(futuresv; dst) 11: end if 12: end while 13: currentsv futuresv 14: end while 15: return currentsv

9. NFA multistriding 2-Stride automaton:  consists of all the possible pairs of original input symbols  each transition is the composition of 2 adjacent transitions of the original. Reducing Execution Time Transition table is need.

10. Experiment (Throughput)

11. Experiment (Memory)