2. CS61C L17 Combinational Logic (1) Chae, Summer 2008 © UCB Albert Chae, Instructor inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #17 – Combinational Logic 2008-7-21

3. CS61C L17 Combinational Logic (2) Chae, Summer 2008 © UCB Review ISA is very important abstraction layer Contract between HW and SW Clocks control pulse of our circuits Voltages are analog, quantized to 0/1 Circuit delays are fact of life Two types of circuits: Stateless Combinational Logic (&,|,~) State circuits (e.g., registers)

4. CS61C L17 Combinational Logic (3) Chae, Summer 2008 © UCB Review State elements are used to: Build memories Control the flow of information between other state elements and combinational logic D-flip-flops used to build registers Clocks tell us when D-flip-flops change Setup and Hold times important Finite State Machines extremely useful

5. CS61C L17 Combinational Logic (4) Chae, Summer 2008 © UCB Review of Signal vocabulary T is the period Period is time from one rising edge to next Unit is seconds 1/T is the frequency Unit is hertz (1/s)

6. CS61C L17 Combinational Logic (5) Chae, Summer 2008 © UCB Accumulator with proper timing reset signal shown. Also, in practice X might not arrive to the adder at the same time as S i-1 S i temporarily is wrong, but register always captures correct value. In good circuits, instability never happens around rising edge of clk.

7. CS61C L17 Combinational Logic (6) Chae, Summer 2008 © UCB Maximum Clock Frequency What is the maximum frequency of this circuit? Max Delay =Setup Time + CLK-to-Q Delay +CL Delay Hint… Frequency = 1/Period

8. CS61C L17 Combinational Logic (7) Chae, Summer 2008 © UCB Pipelining to improve performance (1/2) Timing… Extra Register are often added to help speed up the clock rate. Note: delay of 1 clock cycle from input to output. Clock period limited by propagation delay of adder/shifter.

9. CS61C L17 Combinational Logic (8) Chae, Summer 2008 © UCB Pipelining to improve performance (2/2) Timing… Insertion of register allows higher clock frequency. More outputs per second.

10. CS61C L17 Combinational Logic (9) Chae, Summer 2008 © UCB General Model for Synchronous Systems Collection of CL blocks separated by registers. Registers may be back-to-back and CL blocks may be back-to- back. Feedback is optional. Clock signal(s) connects only to clock input of registers. (NEVER put it through a gate)

11. CS61C L17 Combinational Logic (10) Chae, Summer 2008 © UCB Hardware Implementation of FSM + = ? … Therefore a register is needed to hold the a representation of which state the machine is in. Use a unique bit pattern for each state. Combinational logic circuit is used to implement a function maps from present state and input to next state and output.

12. CS61C L17 Combinational Logic (11) Chae, Summer 2008 © UCB Combinational Logic FSMs had states and transitions How to we get from one state to the next? Answer: Combinational Logic

13. CS61C L17 Combinational Logic (12) Chae, Summer 2008 © UCB Truth Tables 0

14. CS61C L17 Combinational Logic (13) Chae, Summer 2008 © UCB TT Example #1: 1 iff one (not both) a,b=1 aby 000 011 101 110

15. CS61C L17 Combinational Logic (14) Chae, Summer 2008 © UCB TT Example #2: 2-bit adder How Many Rows?

16. CS61C L17 Combinational Logic (15) Chae, Summer 2008 © UCB TT Example #3: 32-bit unsigned adder How Many Rows?

17. CS61C L17 Combinational Logic (16) Chae, Summer 2008 © UCB TT Example #3: 3-input majority circuit

18. CS61C L17 Combinational Logic (17) Chae, Summer 2008 © UCB Administrivia Midterm TODAY 2008-07-21@7-10pm, 155 Dwinelle Bring pencils and eraser! You can bring green sheet and one handwritten double sided note sheet No calculator, laptop, etc. No stress… remember you can get it clobbered

19. CS61C L17 Combinational Logic (18) Chae, Summer 2008 © UCB Logic Gates (1/2)

20. CS61C L17 Combinational Logic (19) Chae, Summer 2008 © UCB And vs. Or review – Dan’s mnemonic AND Gate C A B SymbolDefinition AN D

21. CS61C L17 Combinational Logic (20) Chae, Summer 2008 © UCB Logic Gates (2/2)

22. CS61C L17 Combinational Logic (21) Chae, Summer 2008 © UCB 2-input gates extend to n-inputs N-input XOR is the only one which isn’t so obvious It’s simple: XOR is a 1 iff the # of 1s at its input is odd 

23. CS61C L17 Combinational Logic (22) Chae, Summer 2008 © UCB Truth Table  Gates (e.g., majority circ.)

24. CS61C L17 Combinational Logic (23) Chae, Summer 2008 © UCB Truth Table  Gates (e.g., FSM circ.) PSInputNSOutput 000 0 1010 0000 011100 0000 101001 or equivalently…

25. CS61C L17 Combinational Logic (24) Chae, Summer 2008 © UCB Boolean Algebra George Boole, 19 th Century mathematician Developed a mathematical system (algebra) involving logic later known as “Boolean Algebra” Primitive functions: AND, OR and NOT The power of BA is there’s a one-to-one correspondence between circuits made up of AND, OR and NOT gates and equations in BA + means OR, means AND, x means NOT

26. CS61C L17 Combinational Logic (25) Chae, Summer 2008 © UCB Boolean Algebra (e.g., for majority fun.) y = a b + a c + b c

27. CS61C L17 Combinational Logic (26) Chae, Summer 2008 © UCB Boolean Algebra (e.g., for FSM) PSInputNSOutput 000 0 1010 0000 011100 0000 101001 or equivalently… y = PS 1 PS 0 INPUT

28. CS61C L17 Combinational Logic (27) Chae, Summer 2008 © UCB BA: Circuit & Algebraic Simplification BA also great for circuit verification Circ X = Circ Y? use BA to prove!

29. CS61C L17 Combinational Logic (28) Chae, Summer 2008 © UCB Laws of Boolean Algebra

30. CS61C L17 Combinational Logic (29) Chae, Summer 2008 © UCB Boolean Algebraic Simplification Example

31. CS61C L17 Combinational Logic (30) Chae, Summer 2008 © UCB Canonical forms (1/2) Sum-of-products (ORs of ANDs)

32. CS61C L17 Combinational Logic (31) Chae, Summer 2008 © UCB Canonical forms (2/2)

33. CS61C L17 Combinational Logic (32) Chae, Summer 2008 © UCB Peer Instruction A. (a+b) (a+b) = b B. N-input gates can be thought of cascaded 2-input gates. I.e., (a ∆ bc ∆ d ∆ e) = a ∆ (bc ∆ (d ∆ e)) where ∆ is one of AND, OR, XOR, NAND C. You can use NOR(s) with clever wiring to simulate AND, OR, & NOT ABC 1: FFF 2: FFT 3: FTF 4: FTT 5: TFF 6: TFT 7: TTF 8: TTT

34. CS61C L17 Combinational Logic (33) Chae, Summer 2008 © UCB A. (a+b)(a+b) = aa+ab+ba+bb = 0+b(a+a)+b = b+b = b TRUE B. (next slide) C. You can use NOR(s) with clever wiring to simulate AND, OR, & NOT. ° NOR(a,a)= a+a = aa = a ° Using this NOT, can we make a NOR an OR? An And? ° TRUE Peer Instruction Answer A. (a+b) (a+b) = b B. N-input gates can be thought of cascaded 2-input gates. I.e., (a ∆ bc ∆ d ∆ e) = a ∆ (bc ∆ (d ∆ e)) where ∆ is one of AND, OR, XOR, NAND C. You can use NOR(s) with clever wiring to simulate AND, OR, & NOT ABC 1: FFF 2: FFT 3: FTF 4: FTT 5: TFF 6: TFT 7: TTF 8: TTT

35. CS61C L17 Combinational Logic (34) Chae, Summer 2008 © UCB A. B. N-input gates can be thought of cascaded 2-input gates. I.e., (a ∆ bc ∆ d ∆ e) = a ∆ (bc ∆ (d ∆ e)) where ∆ is one of AND, OR, XOR, NAND…FALSE Let’s confirm! CORRECT 3-input XYZ|AND|OR|XOR|NAND 000| 0 |0 | 0 | 1 001| 0 |1 | 1 | 1 010| 0 |1 | 1 | 1 011| 0 |1 | 0 | 1 100| 0 |1 | 1 | 1 101| 0 |1 | 0 | 1 110| 0 |1 | 0 | 1 111| 1 |1 | 1 | 0 CORRECT 2-input YZ|AND|OR|XOR|NAND 00| 0 |0 | 0 | 1 01| 0 |1 | 1 | 1 10| 0 |1 | 1 | 1 11| 1 |1 | 0 | 0 0 0 0 1 0 1 1 1 0 1 0 1 0 1 1 0 0 1 0 0 1 1 1 1 Peer Instruction Answer (B)

36. CS61C L17 Combinational Logic (35) Chae, Summer 2008 © UCB “And In conclusion…” Pipeline big-delay CL for faster clock Finite State Machines extremely useful You’ll see them again in 150, 152 & 164 Use this table and techniques we learned to transform from 1 to another