1. ELEN 468 Lecture 271 ELEN 468 Advanced Logic Design Lecture 27 Interconnect Timing Optimization II

2. ELEN 468 Lecture 272 Wire Segmenting Faster runtime Better solution quality

3. ELEN 468 Lecture 273 Multiple Buffer Types (v 1, 1, 20) 22 r = 1, c = 1 R b = 1, C b = 1, t b = 1 R b2 = 0.5, C b2 = 2, t b2 = 0.5 R d = 1 v1v1 (v 2, 3, 16) v1v1 (v 2, 1, 12) v1v1 (v 2, 2, 14)

4. ELEN 468 Lecture 274 Using Inverters Less cost

5. ELEN 468 Lecture 275 Handle Polarity - Negative Positive - - - - - -

6. ELEN 468 Lecture 276 Slew Constraints When a buffer is inserted, assume ideal slew rate at its input Check slew rate at downstream buffers/sinks If slew is too large, candidate is discarded

7. ELEN 468 Lecture 277 Capacitance Constraints Each gate g drives at most C(g) capacitance When inserting buffer g, check downstream capacitance. If > C(g), throw out candidate Total cap = 500 ff

8. ELEN 468 Lecture 278 Consider Cost/Power A solution is also characterized by cost w A solution is inferior if it is poor on all of c, q and w At source, a set of solutions with tradeoff of q and w w can be total capacitance or the number of buffers

9. ELEN 468 Lecture 279 Cost-Slack Trade-off

10. ELEN 468 Lecture 2710 Data Organization 0 1 2 3 4 (c 1, q 1 )(c 2, q 2 )(c 3, q 3 ) (c 4, q 4 )(c 5, q 5 )(c 6, q 6 ) (c 7, q 7 )(c 8, q 8 ) (c 9, q 9 )(c 10, q 10 ) (c 0, q 0 ) #buffers inserted Sorted in ascending order of (c, q)

11. ELEN 468 Lecture 2711 Pruning Considering Cost (c i, q i, w i ) is inferior to (c k, q k, w k ) if c i > c k, q i w k 0 1 2 (c 1, q 1 )(c 2, q 2 )(c 3, q 3 ) (c 4, q 4 )(c 5, q 5 )(c 6, q 6 ) (c 0, q 0 ) w Prune order Pruning within a list is same as before

12. ELEN 468 Lecture 2712 Continuous Wire Sizing Min delay wire shape: w(x) = a(e -bx ) x

13. ELEN 468 Lecture 2713 Two Types of Wire Sizing Uniform Wire Sizing (UWS) Wire Tapering (TWS)

14. ELEN 468 Lecture 2714 TWS versus UWS TWS UWS

15. ELEN 468 Lecture 2715 Why Uniform Wire Sizing? Empirically, UWS almost as good as TWS Tapering info hard to give to router Better congestion and space management Extraction, detailed routing, verification? Can do it simultaneously with buffering

16. ELEN 468 Lecture 2716 Wire Sizing to Minimize Weighted Delay Sum Minimize  i t i  i weight, t i Elmore delay to sink i Properties Separability Monotone property Dominance property

17. ELEN 468 Lecture 2717 Wire Sizing: Separability For given wire sizing along a path, optimal wire sizing for each subtree off the path can be carried out independently

18. ELEN 468 Lecture 2718 Wire Sizing: Monotone Property Ancestor edges cannot be narrower than downstream edges

19. ELEN 468 Lecture 2719 Wire Sizing: Dominance Property For each edge, if its width in solution W  its width in solution W’, then W dominates W’ Local refinement: size each edge independently to minimize delay sum while other edges are fixed Assume W* is the optimal solution If W dominates W*, then W still dominates W* after local refinement If W is dominated by W*, then W is still dominated by W* after local refinement

20. ELEN 468 Lecture 2720 Optimal Wire Sizing Maximum width solution Each edge starts with max width Perform local refinement Minimum width solution Each edge starts with min width Perform local refinement Enumerate possibilities between min and max width solutions

21. ELEN 468 Lecture 2721 Wire Sizing to Maximize the Min Slack Separability is not true here Can be solved with dynamic programming Can be integrated with buffer insertion

22. ELEN 468 Lecture 2722 Simultaneous Buffer Insertion and Wire Sizing

23. ELEN 468 Lecture 2723 Driver Sizing

24. ELEN 468 Lecture 2724 Combine Buffering and Driver Sizing Directly? Min delay

25. ELEN 468 Lecture 2725 Impact To Previous Stage Current stagePrevious stage Small load Large load Large delay Small delay CdCd

26. ELEN 468 Lecture 2726 Input Load Penalty Penalty = delay of min delay buffer chain driving C d Min buffer CdCd

27. ELEN 468 Lecture 2727 Driver Sizing Considering Impact to Previous Stage Current stage Previous stage Small load Large load Large delay Small delay CdCd Large penalty

28. ELEN 468 Lecture 2728 Driver Sizing in Van Ginneken’s Algorithm Treat the buffer chain as a part of the net Length = 0 Run van Ginneken’s algorithm with fixed driver and min sized buffer