1. Changbo Long ECE Department, UW-Madison clong@cae.wisc.edu Lei He EDA Research Group EE Department, UCLA lhe@ee.ucla.edu Distributed Sleep Transistor Network for Power Reduction* *Partially sponsored by NSF CAREER Award 0093273, SRC grant HJ-1008 and Intel Corporation

2. Outline Motivation Background DSTN Distributed sleep transistor network (DSTN)  Structure, advantages, modeling and sizing algorithm Experiment results Conclusion and future work

3. Motivation Leakage power will become the dominant power component  Reduced feature size  Increased system integration  more idle modules Leakage reduction techniques  To reduce leakage for active modules Dual threshold voltage assignment for sub-threshold leakage [Mahesh et-al, ICCAD’02] Pin reordering for gate leakage [Lee et-al, DAC’03]  To reduce leakage for idle modules Input vector control [Johnson et-al, DAC’99] Power gating Power gating [Kao et-al, DAC’98][Anis-et al, DAC’02]

4. Motivation PMP System level: use power management processor (PMP) to generate control signals [Mutoh et-al, JSSC’96]  PMP  PMP can be distributed Gate level: use sleep transistors to turns off power supply  Concerned with performance loss and area overhead PMP Sleep g1g1g1g1 gngngngn Virtual GND V dd Sleep tr. Sleep

5. Performance Loss Performance loss  Increase in the propagation delay V st Performance loss is proportional to V st MSSC i st  Maximum Simultaneous Switching Current (MSSC) g1g1g1g1 gngngngn V dd i st

6. MSSC MSSC: MSSC: maximum current in the time domain and the input vector domain g1g1 g2g2 g3g3 g1g1 g2g2 g3g3 i g1 i g2 i g3 Input vector Time MSSC t t t t t t t t i total + + =

7. Area Overhead Area overhead: the sleep transistor area and the routing area of virtual ground wires Design convention: given performance loss , minimize area overhead g1g1g1g1 gngngngn V dd MSSC

8. Related Work Module-based design methodology [Mutoh-et al, JSSC’95 ’96] [Kao-et al, DAC’98] singlelarge  A single and large sleep transistor accommodates entire module [JSSC’96]  Manual sizing  automatic sizing considering discharge patterns [Kao-et al, DAC’98] long  Voltage drop on long virtual ground wires is nontrivial, and results in large area

9. Related Work Module-based design methodology [Mutoh-et al, JSSC’95 ’96] [Kao-et al, DAC’98] singlelarge  A single and large sleep transistor accommodates entire module [JSSC’96]  Manual sizing  automatic sizing considering discharge patterns [Kao-et al, DAC’98] long  Voltage drop on long virtual ground wires is nontrivial, and results in large area Cluster-based design methodology [Anis-et al, DAC’02] minimize peak current  Group gates into clusters and minimize peak current in clusters by clustering algorithms avoid  Insert a sleep transistor for each cluster to avoid long virtual ground wires conflict  Clustering may conflict with time-driven placement

10. Sleep transistor area Area*: Area*: the sleep transistor area ignoring the resistance of virtual ground wires  MSSC module ∑ i MSSC cluster_i  area* module area* cluster  MSSC module < ∑ i MSSC cluster_i  area* module <area* cluster

11. Sleep transistor area Area*: Area*: the sleep transistor area ignoring the resistance of virtual ground wires  MSSC module ∑ i MSSC cluster_i  area* module area* cluster  MSSC module < ∑ i MSSC cluster_i  area* module <area* cluster Area mod Area clu Considering the resistance of virtual ground wires, Area mod > Area clu [Anis-et al, DAC’02] DSTN DSTN has the smallest area  Area DSTN ≈ Area * mod

12. DSTN: Distributed Sleep Transistor Network DSTN DSTN enhances cluster-based design by connecting clusters with extra virtual ground wires Cluster-based design DSTN

13. Current Discharging Balance Reduces Size Cluster-based design DSTN private  Current discharges by its private sleep transistor  large transistor size DSTN DSTN bothprivateneighboring  Current discharges by both private and neighboring sleep transistors  small transistor size

14. Additional Advantages of DSTN Cluster-based design DSTN DSTNNO constraint DSTN introduces NO constraint on placement DSTNsmall Wire overhead of DSTN is small Sleep tr. Additionalwires Additional wires Cluster

15. Entire module  resistance network plus current source Switching current RiRiRiRi R st Modeling of DSTN

16. DSTN/SP DSTN Sizing Problem (DSTN/SP) DSTN/SP minimizedsatisfied  Given DSTN topology, DSTN/SP finds the size for every sleep transistor such that the total transistor area of DSTN is minimized and the performance loss constraint is satisfied for every cluster DSTN Sizing Problem R st =? W=? W=? W=? W=? PL<  R st =? V st <ε R st =? V st <ε R st =? V st <ε Switching current

17. Primary challenge: current source  Dependency between the current sources  Current varies w.r.t. time Secondary challenge: resistance network R st  Given current source, size R st to minimize transistor area while satisfy performance loss constraints Does any algorithms exist in the literature?  No exact solution Close solution for Power/Ground network sizing [Boyd, et-al ISPD’01] special DSTN/SP  We have developed an algorithm based on special properties of DSTN/SP Difficulties of DSTN/SP

18. Properties of DSTN/SP Solutions P1R i =0 P1: Assuming R i =0,   MSSC   : Performance loss constraint, MSSC: Maximum current

19. P2Area DSTN R i P2: given current source, Area DSTN increases when R i increases R i << R st  The increase is limited because R i << R st Area DSTN Area cluster  R i =∞, Area DSTN =Area cluster Properties of DSTN/SP Solutions

20. P3Area DSTN P3: Assuming cluster current and Area DSTN to be constant, to achieve minimum performance loss, Properties of DSTN/SP Solutions

21. Algorithm for DSTN/SP P1P2DSTN P1, P2: Total sleep transistor area of DSTN is determined by   R i   [0.05, 0.5], empirical parameter increases when R i increases P3 P3: Size of each individual sleep transistor is MSSC module MSSC cluster Key is to estimate MSSC module and MSSC cluster

22. MSSC module Estimate MSSC module  Circuit current strongly depends on input vector  The space of input vector increase exponentially with the number of primary input  Genetic algorithm (GA) based algorithm is used [Jiang et-al, TVLSI’00] MSSC cluster Efficient algorithm to estimate MSSC cluster has been proposed in the paper Maximum Current Estimation

23. Cluster-based design without considering placement constraint ∑ i MSSC cluster_i Area cluster  Given a circuit and cluster size, partition gates into clusters such that ∑ i MSSC cluster_i is minimized and Area cluster is minimized in turn Clustering algorithm  Simulated Annealing (SA) Sizing algorithm  Each individual sleep transistor  Total area Base-line Case: Cluster-based Design

24. Experiment Setup Gate level synthesis  Sizing Estimate maximum current for clusters and the entire module Apply the sizing algorithms  Verification Simulate the circuit and obtain the current source by 10,000 random input vectors performance loss KCLKVL Obtain performance loss by solving the resistance network with circuit KCL and KVL equations maximum performance loss Find the maximum performance loss among the performance loss for each input vector Custom layout  Implement a four-bit CLA using 0.35μm technology SPICE  Determine size by SPICE simulation Cluster-based design: each cluster satisfy the performance loss constraint DSTN DSTN: the entire module satisfy the performance loss constraint

25. DSTN 49.8% On average, DSTN reduces total W/L by 49.8% with smaller performance loss Result of Gate Level Synthesis C432 C499 C880 C1355 C1908 C2670 C3540 C5315 C6288 C7552 C432 C499 C880 C1355 C1908 C2670 C3540 C5315 C6288 C7552 Cluster-based DSTN W/L of Sleep Transistors Maximum Performance Loss

26. Each cluster is accommodated by a sleep transistor Sleep transistors Sleep transistors are connected by virtual ground wires Sleep transistors Virtual ground wires Cluster-based design DSTN DSTN Custom Layout in 0.35μm

27. DSTN50x5x DSTN reduces runtime leakage by 50x and 5x  compared to no sleep transistor and cluster-based design, respectively DSTN6.83x6.6% DSTN reduces sleep transistor area by 6.83x with 6.6% smaller performance degradation  compared to the cluster-based design Custom Layout Comparison Leakage current delay Sleep tr. Area Total area No sleep transistor Cluster-based DSTN

28. Conclusion and Future Work DSTN We have proposed DSTN and the sizing algorithm  DSTN  DSTN has reduced area, less leakage current and supply voltage drop Future work  Ideal power/ground network is assumed in this paper DSTNpower/ground network  Investigate the co-design of DSTN and the power/ground network