1. Introduction to CMOS VLSI Design Nonideal Transistors

2. CMOS VLSI Design2 Outline  Transistor I-V Review  Nonideal Transistor Behavior –Velocity Saturation –Channel Length Modulation –Body Effect –Leakage –Temperature Sensitivity  Process and Environmental Variations –Process Corners

3. CMOS VLSI Design3 Ideal Transistor I-V  Shockley 1 st order transistor models V dsat = V gs - V t

4. CMOS VLSI Design4 Ideal nMOS I-V Plot  180 nm TSMC process  Ideal Models –  = 155(W/L)  A/V 2 – V t = 0.4 V – V DD = 1.8 V  =  n C ox (W/L)

5. CMOS VLSI Design5 Simulated nMOS I-V Plot  180 nm TSMC process  BSIM 3v3 SPICE models –very elaborate model derived from the underlying device physics  What differs? Berkeley Short-Channel IGFET Model (BSIM)

6. CMOS VLSI Design6 Simulated nMOS I-V Plot  180 nm TSMC process  BSIM 3v3 SPICE models  What differs? –Less ON current –No square law –Current increases in saturation

7. CMOS VLSI Design7 Velocity Saturation  We assumed carrier velocity is proportional to E-field –v =  E lat =  V ds /L  At high fields, this ceases to be true –Carriers scatter off atoms –Velocity reaches v sat Electrons: 6-10 x 10 6 cm/s Holes: 4-8 x 10 6 cm/s –Better model

8. CMOS VLSI Design8 Velocity Sat I-V Effects  Ideal transistor ON current increases with V 2  Velocity-saturated ON current increases with V  Real transistors are partially velocity saturated –Approximate with  -power law model –I ds  V  –1 <  < 2 determined empirically

9. CMOS VLSI Design9  -Power Model

10. CMOS VLSI Design10 Channel Length Modulation  Reverse-biased p-n junctions form a depletion region –Region between n and p with no carriers –Width of depletion L d region grows with reverse bias –L eff = L – L d  Shorter L eff gives more current –I ds increases with V ds –Even in saturation

11. CMOS VLSI Design11 Chan Length Mod I-V  = channel length modulation coefficient –not feature size –Empirically fit to I-V characteristics

12. CMOS VLSI Design12 Body Effect  V t : gate voltage necessary to invert channel  Increases if source voltage increases because source is connected to the channel  Increase in V t with V s is called the body effect

13. CMOS VLSI Design13 Body Effect Model   s = surface potential at threshold –Depends on doping level N A –And intrinsic carrier concentration n i   = body effect coefficient

14. CMOS VLSI Design14 OFF Transistor Behavior  What about current in cutoff?  Simulated results  What differs? –Current doesn’t go to 0 in cutoff

15. CMOS VLSI Design15 Leakage Sources  Subthreshold conduction –Transistors can’t abruptly turn ON or OFF  Junction leakage –Reverse-biased PN junction diode current  Gate leakage –Tunneling through ultra-thin gate dielectric  Subthreshold leakage is the biggest source in modern transistors

16. CMOS VLSI Design16 Subthreshold Leakage  Subthreshold leakage exponential with V gs  n is process dependent, typically 1.4-1.5

17. CMOS VLSI Design17 DIBL  Drain-Induced Barrier Lowering –Drain voltage also affect V t –High drain voltage causes subthreshold leakage to ________.

18. CMOS VLSI Design18 DIBL  Drain-Induced Barrier Lowering –Drain voltage also affect V t –High drain voltage causes subthreshold leakage to increase.

19. CMOS VLSI Design19 Junction Leakage  Reverse-biased p-n junctions have some leakage  I s depends on doping levels –And area and perimeter of diffusion regions –Typically < 1 fA/  m 2

20. CMOS VLSI Design20 Gate Leakage  Carriers may tunnel thorough very thin gate oxides  Predicted tunneling current (from [Song01])  Negligible for older processes  May soon be critically important

21. CMOS VLSI Design21 Temperature Sensitivity  Increasing temperature –Reduces mobility –Reduces V t  I ON ___________ with temperature  I OFF ___________ with temperature

22. CMOS VLSI Design22 Temperature Sensitivity  Increasing temperature –Reduces mobility –Reduces V t  I ON decreases with temperature  I OFF increases with temperature

23. CMOS VLSI Design23 So What?  So what if transistors are not ideal? –They still behave like switches.  But these effects matter for… –Supply voltage choice –Logical effort –Quiescent power consumption –Pass transistors –Temperature of operation

24. CMOS VLSI Design24 Parameter Variation  Transistors have uncertainty in parameters –Process: L eff, V t, t ox of nMOS and pMOS –Vary around typical (T) values  Fast (F) –L eff : ______ –V t : ______ –t ox : ______  Slow (S): opposite  Not all parameters are independent for nMOS and pMOS

25. CMOS VLSI Design25 Parameter Variation  Transistors have uncertainty in parameters –Process: L eff, V t, t ox of nMOS and pMOS –Vary around typical (T) values  Fast (F) –L eff : short –V t : low –t ox : thin  Slow (S): opposite  Not all parameters are independent for nMOS and pMOS

26. CMOS VLSI Design26 Environmental Variation  V DD and T also vary in time and space  Fast: –V DD : ____ –T: ____ CornerVoltageTemperature F T1.870 C S

27. CMOS VLSI Design27 Environmental Variation  V DD and T also vary in time and space  Fast: –V DD : high –T: low CornerVoltageTemperature F1.980 C T1.870 C S1.62125 C

28. CMOS VLSI Design28 Process Corners  Process corners describe worst case variations –If a design works in all corners, it will probably work for any variation.  Describe corner with four letters (T, F, S) –nMOS speed –pMOS speed –Voltage –Temperature

29. CMOS VLSI Design29 Important Corners  Some critical simulation corners include PurposenMOSpMOSV DD Temp Cycle time Power Subthreshold leakage Pseudo-nMOS

30. CMOS VLSI Design30 Important Corners  Some critical simulation corners include PurposenMOSpMOSV DD Temp Cycle time, timimg specification. conservative SSSS Power,DC power comsumption, race conditions,etc FFFF Subthreshold leakage, noise analysis FFFS Pseudo-nMOS and ratioed circuits SFFF