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Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation Lei He 1, Andrew Kahng 2, King Ho Tam 1, Jinjun.

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Presentation on theme: "Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation Lei He 1, Andrew Kahng 2, King Ho Tam 1, Jinjun."— Presentation transcript:

1 Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation Lei He 1, Andrew Kahng 2, King Ho Tam 1, Jinjun Xiong 1 1 Univ. of California, Los Angeles 2 Blaze DFM, Inc. & Univ. of California, San Diego Sponsors: 1 NSF CAREER, SRC, UC MICRO sponsored by Analog Devices, Fujitsu Lab., Intel and LSI Logic, IBM Faculty Partner Award; 2 MARCO Gigascale System Research Center, NSF.

2 Existing Work on Variation- Aware Buffer Insertion Buffer insertion for length variation [Khandelwal-ICCAD] Variation sources from difference between estimated and actual wire length Buffer insertion for process variation [Xiong- DATE] Random L eff and interconnect width variations Brute-force numerical manipulation of joint probability density functions (JPDFs), not efficient

3 Buffer Insertion and Wire Sizing (SBW) with Process Variations Variations models L eff – random variation In reality, 50% systematic and 50% random Interconnect RC – systematic variation due to Chemical Mechanical Planarization (CMP) Random component of global interconnect variation on performance is insignificant in general Efficient variation-aware algorithms Table-based capacitance and fill insertion under CMP Efficient pruning to deal with random variation

4 Outline SBW and fill insertion (SBWF) under CMP variation Modeling RC variation CMP-aware SBW and fill insertion algorithm Experiment: CMP-aware vs CMP-oblivious Extension to L eff variation Conclusion

5 Chemical Mechanical Planarization (CMP) Metallization process Etch trenches Deposit Cu bulk Cu removal by CMP Dishing/Erosion Loss of Cu thickness due to over-polishing Fix: dummy fill insertion for more uniform Cu loss Dummy fill insertion Increase coupling cap

6 Chemical Mechanical Planarization (CMP) Dishing and erosion lead to Up to 31.7% increase in resistance No change in capacitance Fill insertion [He-SPIE] can lead to 1.5x increase in coupling capacitance (C c ) 2% increase in total capacitance (C s ) Can be up to 10% increase if fill pattern is not optimized width (μm)space (μm)R w/CMPC c w/CMPC s w/CMP 0.240.95+28.7%+33.1%-0.11% 2.610.95+30.6%+26.3%-1.35% 4.750.95+31.4%+26.5%-0.23% 0.241.43+28.8%+142.7%+1.88% 2.611.43+30.9%+141.8%+0.36% 4.751.43+31.7%+148.8%-0.69%

7 Problem Formulation RAT = 1800ps C = 18fF RAT = 1200ps C = 21fF RAT = 2500ps C = 25fF RAT = 2000ps C = 10fF RAT = 900ps C = 30fF RAT = 1200ps C = 2fF RAT = 2000ps C = 15fF RAT = 2200ps C = 8fF Reff = 100Ω ρ2ρ2 ρ1ρ1 ρ6ρ6 ρ5ρ5 ρ4ρ4 ρ3ρ3 RAT opt

8 CMP-aware RC Parasitics Optimal (min-Cx) dummy fill pattern insertion Pre-compute dummy fill pattern by enumeration [He-SPIE] Tabulate both cap and fill pattern, indexed by wire width/space and fill amount Post-dummy fill dishing/erosion calculation Using Tugbawa-Boning’s model from MIT [Tugbawa-thesis] Input: effective metal density, wire width/space

9 SBWF Algorithm Extended dynamic programming [van Ginneken-ISCS] CMP model is deterministic Amount of variation calculated from metal features Use CMP-aware RC Prune sub-optimal/invalid partial solutions Inferior: C inf > C n & AT int < AT n Rise-time violation: D subtree > D bound

10 Experiment Experimental settings ITRS 65nm (interconnect) & BSIM 4 (device) RAT at sinks = 0, T r < 100ps SBW + Fill Solving SBW using CMP-oblivious RC, i.e. no dishing/erosion/fill insertion Risetime constraint set to 83ps during optimization to get solution that meets the T r < 100ps constraint Solution to be verified after under CMP-aware RC SBWF Simultaneous buffering, wire sizing and fill insertion

11 Experiment: SBW + Fill vs SBWF r1 – r5: benchmarks from [Tsay-TCAD] SBWF improves over SBW + Fill design 1. by 1.0% arrival time on average 2. by 5.7% power per switch SBW + FillSBWF net# sinksSrc AT (ps)Power (pJ)Runtime (s)Src AT (ps)Power (pJ)Runtime (s) r1267-243726667-2427 (0.4%)250 (-6.2%)86 r2598-3080531173-3044 (1.2%)486 (-8.5%)193 r3862-3684662207-3636 (1.3%)613 (-7.4%)257 r41903-53721358389-5319 (1.0%)1243 (-8.5%)459 r53101-60052025512-5960 (0.7%)1865 (-7.9%)727

12 Outline SBW and fill insertion (SBWF) under CMP variation Modeling RC variation CMP-aware SBW and fill insertion algorithm Experiment: CMP-aware vs CMP-oblivious Extension to L eff variation Conclusion

13 Statistical Buffer Insertion under Random L eff Variation L eff variation leads to delay variation Pick the solution with the desired distribution Objective in this work: maximize “required arrival time” at the source for majority of dies Delay = T = 1 Cumulative Probability RAT RAT @ 90% This portion subject to AT optimization

14 Modeling Buffer Delay due to L eff Variation Buffer characterization by Input capacitance (C in ) insensitive to L eff variation For total L eff of a buffer at the largest 1% corner, input capacitance only increases by 3% Output resistance (R eff ) and intrinsic delay (D buf ) sensitive to L eff and their variations are correlated Joint probability density function: PDF R,d (R eff, D buf ) Delay with load L buf : D load = L buf · R eff + D buf Modeled by cumulative distribution functions (CDFs) CDF d(L) (D load ) =

15 Challenges in Statistical Buffer Insertion Problem Efficient manipulation of statistical calculation Arrival time as a random variable for optimization Captured by CDF Calculation is slow by brute-force manipulation Our approach: piece-wise linear (PWL) modeling Pruning rules to remove sub-optimal options Deterministic AT 1 > AT 2 and L 1 < L 2 – establishes total order Probabilistic P(AT 1 > AT 2 Λ L 1 < L 2 ) – only forms partial order  eg. P(AT 1 > AT 2 ) = 0.6: sol 1 >> 2, but with a low probability

16 Statistical Operations in Buffer Insertion Problem Buffer insertion-related timing calculation Adding a wire AT i = AT j – r*d ij *L j – 0.5*r*c*d ij 2 Adding a buffer AT buf = AT i – d – R eff *L i Merging two branches AT i = min(AT j, AT k ) Key operations on variables Statistical Statistical subtraction (addition) and minimum (maximum) + ij + ibuf j k i min?

17 Statistical Operations in Buffer Insertion Problem Add: z = x + y (if x and y independent) CDF z (t) = PDF x (t) ⊕ CDF y (t) Max: z = max(x, y) (if x and y independent) CDF z (t) = CDF x (t) * CDF y (t) Independence of random variables Adding wire Adding buffer Merging branches + ij constant i + buf uncorrelated j + k i from independent subtrees

18 Modeling Cumulative Distribution Functions (CDFs) CDF: PWL curve [Devgan-ICCAD] Statistical addition (convolution) and maximum (multiplication) has closed-form solutions under PWL modeling FAST!! Sampling at pre-set percentile points on the y-axis is performed after operations to keep PWL form PDF: Piecewise constant (PWC) curve Obtained by differentiating the PWL of CDF

19 Key to Pruning: Definition of Dominance CDF Dominance Dominated curve completely on the L.H.S. of some others Yield-cutoff dominance Compare the AT only at the target timing yield rate (Y t ) CDF Dominance Yield-cutoff dominance

20 CDF Pruning Accurate as it does not drop options that may lead to the optimal solution Ineffective as it does not form total-order ⊕ or * = dominated still dominated Not dominating one another under CDF Dominance, i.e., must keep both curves

21 Yield-cutoff Pruning No partial-ordering issue, i.e. effective Experimentally proven to achieve same accuracy as CDF Pruning CDF PruningYield-cutoff Pruning TestcaseMean (ps)SD (ps)Δ MeanΔ SD Line-65693380% 5-sink-115435050%1.2% 6-sink-91894370.03%0.002% log(runtime) (s) wire length (um) CDF Pruning Yield-cutoff Pruning

22 Experimental Settings Experimental settings Target timing yield rate at 90% i.e. maximize the AT of 90% of dies Risetime at any node has 99% chance < 100ps SBW+Fill as our baseline CMP as after-thought and no L eff variation Requires over-constrained slew rate ratio 0.75 i.e. design under 75ps to satisfy risetime constraint vSBWF: SBWF + L eff variation

23 Definition of Timing Yield AT with 90% timing yield for vSBWF Yield rate at the same AT of SBW+Fill is only 25.1%

24 Experiment: SBW+Fill vs vSBWF Timing yield SBW+Fill: 45.7% on average vSBWF: 90% as targeted Runtime of vSBWF 8.3x that of SBW+Fill SBW+FillvSBWF testcase# sinksyield (%)runtime (s)yield (%)runtime(s) r12670.1%10190%1054 r25986.7%21390%2126 r38625.9%27790%2140 r419039.0%60790%4429 r531011.5%97290%7440

25 Conclusion Developed SBWF: CMP-aware buffering, wire sizing and fill insertion Reduced 1.0% delay and 5.7% power Extended SBWF to L eff random variation Proposed efficient yet effective yield-cutoff pruning rules Improved timing yield rate by 44.3% Finished largest example (3000+ sinks) in 2 hours

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