1. 1 Synthesis For CMOS/PTL Circuits Congguang Yang Maciej Ciesielski Dept. of Electrical & Computer Engineering University of Massachusetts, Amherst Sponsored by NSF

2. 2 Traditional logic synthesis (SIS) –use factored forms, algebraic factorization: a(b+c) –boolean formulas treated as polynomials: F = ac + bc + ad + bd = (a + b) (c + d) –weak Boolean factorization capability F = a + bc = (a + b)(a + c) …. cannot be found easily –good for AND/OR, difficult to identify XOR and MUX logic Our approach –based on BDD representation of logic –truly Boolean operations, Boolean algebra rules applied: a + a = a, a * a’ =0, a * 1 = a, a * 0 = 0, etc –can easily identify XOR, MUX structures –very fast Motivation

3. 3 BDD-based Logic Decomposition Simple dominators –Algebraic AND, OR, XOR decomposition Generalized dominators –Boolean AND, OR, XOR decomposition Cofactor, single/super node –Simple/complex MUX Observation: BDD structure reveals functional decomposition. Identify Dominators (BDD structures)  different logic decompositions

4. 4 01 D = a + b b a 01 F = a + bc c a b 01 Q = a + c c a F = a + bc = (a + b)(a + c) = * Boolean AND/OR decomposition

5. 5 Boolean AND decomposition - example g d e a f b b cc Q 1 DC 0 minimize g d e a Q 1 0 Q = ag + d + e a f b b cc 0 0 D 1 reduce D = af + b + c a f b c 0 D 1 g d e a f b b cc F 1 0 0 F = D Q 3. Compute Q from F, minimize Q 1. Find a cut in BDD of F 2. Create divisor D (generalized dominator), reduce D

6. 6 XOR Decomposition – Role of X-dominator Identify a node (x-dominator) with complement and regular edges Split node function into f and f’ Compose the two parts with XOR General idea:

7. 7 MUX Decomposition 1 01 b a 0 F d c F 1 d b a c 0 F v f g 01 F v g f Simple MUX Complex MUX Identify exactly two nodes covering all paths to 1, 0 Connect one node to 1, the other to 0 Upper portion defines control h

8. 8 Decomposition of Multiple-output Functions Build BDD for each output Decompose each BDD Construct factoring trees Identify logic sharing

9. 9 Logic balancingLogic balancing Reduction of long transistor chainsReduction of long transistor chains Fanout reductionFanout reduction Application to CMOS/PTL Logic Synthesis

10. 10 Application to CMOS/PTL Logic Synthesis Map the decomposed logic onto CMOS and PTLMap the decomposed logic onto CMOS and PTL –Preserve XOR’s and MUXes for PTL –Use CMOS to provide buffering for PTL –New technology mapping techniques needed (tree-based mappers are inadequate) Develop PTL cell libraryDevelop PTL cell library (with and w/out buffers)(with and w/out buffers) Extract XOR’s and MUXes during BDD decomposition Extract XOR’s and MUXes during BDD decomposition

11. 11 Preliminary Results – XOR Intensive Logic Comparison with SIS and [tsai’96] # XOR’s: after/before technology mapping SIS mapper used (lower cost assigned to XOR gates)

12. 12 Application to FPGA Synthesis Very fast (orders of magnitude)Very fast (orders of magnitude) Good for rapid prototypingGood for rapid prototyping Good results in terms of logic density and wiringGood results in terms of logic density and wiring 30 – 40% improvement compared to SIS + FlowMap30 – 40% improvement compared to SIS + FlowMap Open problems:Open problems: Incremental synthesisIncremental synthesis Specialized decomposition specifically for FPGAsSpecialized decomposition specifically for FPGAs