1. Lab Lecture 5 Aahlad

2. Process Statement-A Review…. Syntax process (sensitivity_list) declarations; begin sequential statement;... end process;

3. entity class is port(A,B,C: in std_logic; D,E : out std_logic ); end entity; architecture beh of class is begin process (A) begin if (A=‘1’) then D<=A and B; E <= B and C; end if; end process; end beh;

5. entity class is port(A,B,C: in std_logic; D,E : out std_logic ); end entity; architecture beh of class is begin process (A,B) begin if (A=‘1’) then D<=A and B; E <= B and C; end if; end process; end beh;

7. Process Statement-A Review…. Process (Clock) If clock’event and clock=‘1’ them  Check for a event on clock and then check if clock = ‘1’ i.e we are checking for the rising edge of the clock.

8. IP Cores An IP (Intellectual Property) core is a block of HDL code that other engineers have already written to perform a specific function. It is a specific piece of code designed to do a specific job. IP cores can be used in a complex design where an engineer wants to save time.

9. IP Cores As with any engineering tool, IP cores have their advantages and disadvantages. Although they may simplify a given design, the engineer has to design the interfaces to send and receive data from this “black box”. Also, while an IP core may reduce design time, the engineer frequently has to pay for the right to use the core. ISE offers a few IP Cores.

10. IP Cores

15. After generating the IP Core create a new file  copy the libraries and entity (change the name of the entity) from add_sub.vhd (created by IP Core) file to your new file. Open add_sub.vho (created by IP Core) and copy paste the component instantiation in the new file. Save the new file and add it to project.

16. library IEEE;------Your vhdl file use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library UNISIM; library XilinxCoreLib; entity adder_subtracter is port ( A: IN std_logic_VECTOR(3 downto 0); B: IN std_logic_VECTOR(3 downto 0); ADD: IN std_logic; Q: OUT std_logic_VECTOR(4 downto 0); CLK: IN std_logic); end adder_subtracter;

17. architecture behavioral of adder_subtracter is component add_sub ---created by IP Coregen.vho file port ( A: IN std_logic_VECTOR(3 downto 0); B: IN std_logic_VECTOR(3 downto 0); ADD: IN std_logic; Q: OUT std_logic_VECTOR(4 downto 0); CLK: IN std_logic); end component; attribute syn_black_box : boolean; attribute syn_black_box of add_sub: component is true; begin UUT : add_sub ----created by IP Coregen.vho file port map ( A => A, B => B, ADD => ADD, Q => Q, CLK => CLK); end behavioral;