1. Layout-based Logic Decomposition for Timing Optimization Yun-Yin Lien* Youn-Long Lin Department of Computer Science, National Tsing Hua University, Hsin-Chu, Taiwan 300, ROC *Global Unichip Corporation

2. UniChip Outline  Introduction  Motivation  Previous Work  Proposed Methods  Experimental Results  Conclusions and Future Works

3. UniChip Timing meet? No Yes Finished Design House Logic Synthesis Placement and Routing ASIC Vender Introduction  Traditional ASIC design flow

4. UniChip Design House Logic Synthesis ASIC Vender Initial Placement and Routing Layout-based Logic Synthesis Incremental Placement and Routing Incremental Placement and Routing Extracted wire RC Changed netlist, ECO information Extracted wire RC Timing meet Timing not meet Optimization or Finish Design Flow Considering Layout

5. UniChip Layout-based Logic Synthesis  Some existing techniques  Gate Sizing  Buffer Insertion  Rewiring  Logic Restructuring  Logic Decomposition  We combine Gate Sizing, Buffer Insertion and Logic Decomposition

6. UniChip The effect of Gate Sizing is limited by the library Library Observation 1

7. UniChip Inputs to a cell can be divided into critical part and non-critical part Observation 2

8. UniChip Motivation  Break the limitation of gate sizing  Increase gate sizing opportunity  Logic decomposition for gate sizing … rule1  Speed up critical path  Divide critical inputs and non-critical inputs of a cell  Logic decomposition for speeding up critical path … rule2

9. UniChip Previous Work  Logic Decomposition -- Singh et al.  During technology mapping  Simple delay model  Retiming and resynthesis[SIS] -- Malik et al.  Partition -- Beardslee et al.  Logic restructuring and buffer insertion -- Jiang et al.

10. UniChip Initial Placement and Routing Initial Placement and Routing Layout-based Logic Synthesis Layout-based Logic Synthesis Incremental Placement and Routing Incremental Placement and Routing Delay Calculator Path Extraction Delay Calculator Path Extraction Area Reduction Gate Downsizing Buffer Removal Area Reduction Gate Downsizing Buffer Removal Buffer insertion Gate sizing Logic Decomposition Buffer insertion Gate sizing Logic Decomposition ECO information Wire RC CircuitLibrary Timing meet Proposed System Flow

11. UniChip Logic Decomposition  Cell Selection  Cell Substitute Generation  Candidate Selection  Cell Substitution

12. UniChip Cell Selection  Cell Selection Criteria  Cell inputs consists of critical part and non- critical part  No gain in sizing up the cell  cell had been sized up to the largest template before this iteration  cell has negative gate sizing score in this iteration

13. UniChip Cell Substitute Generation  two-level substitutes  For rule1...

14. UniChip Cell Substitute Generation(cont.)  For rule2

15. UniChip Candidate Selection  Criteria  The longest path delay candidate < The longest path delay original  The longest path delay candidate is the smallest one among all substitutions

16. UniChip Candidate Selection (cont.)  Assign each cell of group B to the largest template for rule1, smallest template for rule2  Assign location on layout  cell B k+1 = cell B  cell B 1 ~B k nearby cell B

17. UniChip Candidate Cell Substitution  Sort inputs of G by criticality  Get the proper size of each cell

18. UniChip D1 D2 D Replace D2 Insert D2 D1 Initial Placement and Routing Initial Placement and Routing Layout-based Logic Synthesis Layout-based Logic Synthesis Incremental Placement and Routing Incremental Placement and Routing Delay Calculator Path Extraction Delay Calculator Path Extraction ECO information Wire RC Incremental P & R

19. UniChip Unmapped circuit SIS: Map for Speed Logic Gate Sizing SIS: Map for Speed Logic Gate Sizing TimberWolfSC: Initial Placement and Routing TimberWolfSC: Initial Placement and Routing G:Gate Sizing B:Buffer Insertion D:Logic Decomposition Layout-based Optimization System Layout-based Optimization System Final Layout TimberWolfSC: Final Placement and Routing TimberWolfSC: Final Placement and Routing SISGS Experimental Procedures

20. UniChip Experimental Results  Average delay reduction  G:16.39%  G+D:24.24%

21. UniChip Experimental Results (cont.)  Average area increment  G:2.50%  G+D:4.88%

22. UniChip Experimental Results (cont.)  CPU Time

23. UniChip Experimental Results(cont.)  Average delay reduction  G+B:19.96%  G+D:24.24%  G+B+D:25.43%

24. UniChip Conclusions  Combine logic decomposition with gate sizing (compare with SISGS )  Only Gate Sizing  average delay reduction is 16.39%  maximum delay reduction is 32.58%  Gate Sizing + Rule1  average delay reduction is 20.29%  maximum delay reduction is 41%  Gate Sizing + Rule2  average delay reduction is 23.24%  maximum delay reduction is 54%

25. UniChip Discussion  Logic Decomposition  Suitable for circuits with decentralized critical paths  Useful for library with high variety in the number of template for each gate  The effectiveness of Gate Sizing is limited by the library and the persistent netlist structure  Buffer insertion is effective for nets with high fanout counts

26. UniChip Future Work  Design a filter program which can analyze the input circuit first  Find suitable optimized techniques  Save program run time  Interconnect-Centric Methodology