1. [M2] Traffic Control Group 2 Chun Han Chen Timothy Kwan Tom Bolds Shang Yi Lin Manager Randal Hong Wed. Sep 29 Overall Project Objective : Dynamic Control The Traffic Lights

2. Status  Design Proposal  Chip Architecture  Behavioral Verilog Implementation  Size estimates (Refined)  Floorplanning (Refined)  Behavioral Verilog simulated  Gate Level Design  Component Layout/Simulation  Chip Layout  Complete Simulation

3. Traffic Flows Sensors (Blue) To detect the car entered Sensors (Red) To detect the car leaved ARM 1 ARM 2

4. Traffic Light Flow Whenever pedestrian push the button, then this light will insert in the end of this cycle. ARM 1 ARM 2 Red GreenY Green (S traight + R ight )YRed+Green(L eft ) Red Y Green (S traight + R ight )YRed+Green(L eft )Y Phase A Phase C Phase BPhase APhase B ARM1 ARM2 PED We define three phases (A,B,C) for different operations.

5. SW – Switch light G – Green R – Red Y – Yellow T – Time for Yellow PED – Pedestrian SW (1bit) ARM (1bit) PED(1bit) CLK ARM1 [1:0] FSM Initial G.R Y.R R+L eft.R Y.R R.G R.Y R.R+L eft PED SW = 0 SW = 1 T < 2 T = 2 SW = 1 SW =0 T<10 PED = 1 T = 2 PED = 1 T = 2 T<= 2 SW = 0 T=15 T = 2 PED = 0 T = 2 PED = 0 ARM = 0ARM = 1 FSM For Lights Clear (1bit) ARM2 [1:0] PED(1bits) Blink T=10 T < 5 Complete(1bits)

6. Hold until n 1 or n 2 changes Light favors n 1 or n 2 ? n1n1 n2n2 T<r 1 ? T<r 2 ? T>= R 1 ?T>= R 2 ? n 1 =0? n 2 =0? f 1 <=0? f 2 <=0? Switch Light Reset T = 0 No Yes No Yes No Light favors arm 1 or arm 2 ? n1n1 n2n2 T<r left ? T>= R left ? No Yes No Yes No n 1 not change in T = 5? No Control reset Pedestrian For Green light For Red + Left T>= R p ? Yes No For Pedestrian n 2 not change in T = 5? n 1, n 2 :# of cars T :Time spent in this phase R i, r i : Max. and Min. time for each phase f i : the control function f 1 = α 1 *n 1 + β 1 – n 2 f 2 = α 2 *n 2 + β 2 – n 1

7. FPU Multiplier

8. FPU Mult  Adder  Add exps  Mult  Multiply significants  Mtmp + Leadshift  Determine possible ovf and normalize  SigshiftY, SigY, SignY  Rounding more or less  Determines sign  Special Cases – NaN/inf

9. FPU Multiplier Hardware  4-bit adder(RCA) – 112  Sequential Multiplier(8-bit)  8-bit RCA – 224  8 2-input AND gates – 48  3x8bit Registers – 336  4-bit decrementer – 142  17 Bit Barrel Shifter - 5780!!!(Programmable)  12 bit comparator – 408  Other Logic gates – 14

10. FPU Mult. Hardware cont.  Special Case Logic(NaN/Inf)  3x4-bit comparators – 0* (use prev 12 bit comp)  2x7-bit comparator – 0*  12-bit comparator – 0*  2x12-bit MUX – 96  Other logic gates – 56  Overflow Mult Logic  3x4 bit comparator – 0*  12 bit comparator – 0*  2x 2-bit MUX – 16  Other Logic – 60  1x 8-bit MUX – 32  1x12-bit MUX – 48

11. FPU Mult Hardware cont.  sigY  8-bit incrementer – 112  4-bit incrementer - 56  2x12-bit MUX – 96  8-bit comparator - 0*  12-bit Shifter – 0*  1-bit MUX – 4  4-bit mux - 16  Other Logic – 12  SignY  12-bit comparator – 0*  4-bit comparator – 0*  Leading Zeroes 12-bit – 340

12. FPU Mult. Hardware cont.  Mtmp  16-bit MUX – 64  4-bit MUX – 16  1-bit MUX - 4  4 bit adder(RCA) – 112  16 Bit shifter – 0*  Other logic -86  Leadshift  2x4-bit Comparator – 0*  2x16-bit shifter – 0*  2x16-bit MUX – 128  2x4-bit MUX – 32  Other logic -34  Total  8484(2704 excluding barrel shifter) Transistors with some reuse(Reg/Mux not added for reuse operations)

13. Addition/Subtraction Shifting Shift significants and alter exp Inv Signal if necessary(Add/Sub) Does Add/Sub in Add/Sub Does sign Recognition Make_pos Possibly a negative significant, thus make it a positive significant if necessary otherwise filter threw Overflow Rounding Special Cases

14. FPU Add/Sub hardware  Special Cases-0*  Other Logic – 40  Shifting - 17-bit barrel shifter – 0* - 5x 5-bit comparators – 0* - Other logic – 600 (lot of gate logic to choose shifting and get diff of exp(with adders)) - LeadingZeros12 – 0* - 3x8-bit adder

15. FPU Add/Sub hardware  Add/Sub  12-bit RCA – 336  Logic Gates/Arrays – 300  2:1 12-bit MUX – 48  MakePos  12-bit RCA – 336  Logic Gates – 426  Zero Res  12-bit comparator – 0*  Logic Gates – 208

16. FPU Add/Sub Hardware  Overflow Manipulation  2x17 bit barrel-shifter – 0*  4-bit RCA Adder -112  4-bit Comparator – 0*  2:1 12 bit MUX – 48  Other logic to determine ovf – 300  Rounding  2x17 bit barrel-shifter -0*  Other logic - 576  2x12-bit adder – 672  4-bit adder -112  4-bit comparator – 0*s  Total -3474

17. FPU Total Transistor Count  Addition/Sub – 3474  Multiplier – 8484  Extra Muxing + Registers for Reuse – 1000?  Total- 12958  Save more adders?

18. Block Diagram AccumRegConv.F 8 8 12 ENTER 12 8 AccumRegConv.F 8 8 12 OUT or LEFT 12 8 s0,s1: X2 q0,q1: X2 Reg X 10 12 Reg X 10 2:1 MUX 120 12 X 10 12 X 9 12 X 1 q0 q1 12 β n1 n0 12 Q_len12 16:1 MUX 4 Sel 12 s0 s112 Sel 4 N_avg αn 0 -n 1 αn 0 q 0 -s 0 q 1 -s 1 α0α0 α1α1 Q(αn 0 -n 1 ) FPU 2 Sel_FPU 1:16 De-MUX 4 Sel 12192 Reg. 12bit n0 n1 ROM 12 β 2:1 MUX temp 12 n_avg Q(αn 0 -n 1 ) q 1 -s 1 q 0 -s 0 αn 0 αn 0 -n 1 12 F ROM 12 User Input 2:1 MUX Reg 12 α0,α1:X2 ROM User Input 1/Q Reg User Input R,r 64 12 8 X 8 : to comparator R,r, RL,rl for arm1&2 12 ½ 2:1 MUX Reg PED PED Input 11 Reg PED CLK 11 to comparator β 8 X 8 8:1 MUX 8 8 INT. Compar 8 X 2 8 8 FP. Compar 2:1 MUX 1 1 FSM SW ARM PED CLK Clear FSM 1 1 1 1 1 Complete 1 ARM 1 ARM 2 PED. 1 2 2 ½

19. AccumRegConv.F 8 8 12 ENTER 12 8 AccumRegConv.F 8 8 12 OUT or LEFT 12 8 s0,s1: X2 q0,q1: X2 Reg X 10 12 Reg X 10 2:1 MUX 120 12 X 10 12 X 9 12 X 1 q0 q1 12 β n1 n0 12 Q_len12 16:1 MUX 4 Sel 12 s0 s112 Sel 4 N_avg αn 0 -n 1 αn 0 q 0 -s 0 q 1 -s 1 α0α0 α1α1 Q(αn 0 -n 1 ) FPU 2 Sel_FPU 1:16 De-MUX 4 Sel 12192 Reg. 12bit n0 n1 ROM 12 β 2:1 MUX temp 12 n_avg Q(αn 0 -n 1 ) q 1 -s 1 q 0 -s 0 αn 0 αn 0 -n 1 12 F ROM 12 User Input 2:1 MUX Reg 12 α0,α1:X2 ROM User Input 1/Q Reg User Input R,r 64 12 8 X 8 : to comparator R,r, RL,rl for arm1&2 12 ½ 2:1 MUX Reg PED PED Input 11 Reg PED CLK 11 to comparator β 8 X 8 8:1 MUX 8 8 INT. Compar 8 X 2 8 8 FP. Compar 2:1 MUX 1 1 FSM SW ARM PED CLK Clear FSM 1 1 1 1 1 Complete 1 ARM 1 ARM 2 PED. 1 2 2 ½ T : 3336 X 2 T : 334 T : 2072 T : 14 T : 1680 X 2 T : 96 T : 1440X2 T : 1440 T : 12kT : 1680 T : 166 T : 64 X 2 T : 448 X 2 T : 5000 T : 460 T : 344

20. Transistor Count Estimates DevicesNumber of Transistors FPU12,000 Registers5,824 MUX6240 Flow Control FSM5,000 Light Control FSM460 Convert to FP6000 ROM~1000 (?) Comparator688 Total37212

22. Input Get q0 q1 s0 s1 Avg. q ½, Q_L FPUOutput Reuse F, Ni Give R,r Input PED, CLK Compare T Control Light