1. Ugur Kalay, Marek Perkowski, Douglas Hall Universally Testable AND-EXOR Networks Portland State University Speaker: Alan Mishchenko

2. 2 Agenda Introduction –desired properties of a test set –testing AND and EXOR gates –test scheme proposed by Reddy Testing Two-level AND-EXOR Networks –implementation of the new testing scheme –experimental results Testing Multi-Level AND-EXOR Networks –extending the scheme for multi-level circuits Conclusions and Directions of Future Research

3. 3 100% Fault Coverage –no fault simulation Minimal (as few tests as possible) –shorter testing time Universal (does not depend on the circuit) –portability of the pattern generator –reduced engineering Regular (test patterns have certain structure) –simpler pattern generator Good Scalability –easy pattern generator expandability Introduction Requirements for a Test Set

4. 4 Introduction Testing AND gate Tests Faults 1234 abcsa0sa1sa0sa1sa0sa1sa0sa1 111++++ 011++ 101++ 110++ 1 2 3 4 a b c

5. 5 Introduction Testing EXOR gate Inputs  Class AClass B abg1g1 g2g2 g3g3 g4g4 g5g5 g6g6 g7g7 g8g8 g9g9 g 10 g 11 g 12 g 13 g 14 g 15 g 16 000000111001001111 011000111110101000 101011011011000010 110001001010111011 abFaults detected 00g 5, g 6, g 7, g 10 01g 2, g 3, g 4 10g 8, g 11 11g9g9 a g b

6. 6 Reddy’s Positive Polarity Reed-Muller Testing Scheme Example: f = x 1 x 2  x 1 x 3  x 1 x 2 x 3 x 0 x 1 x 2 x 3 x 0 x 1 x 2 x 3 0 0 0 0 - 0 1 1 T 1 = 0 1 1 1 T 2 = - 1 0 1 1 0 0 0 - 1 1 0 1 1 1 1 -: don’t care * Large expression leads to long EXOR cascade Introduction * 100% Single Stuck-at Fault Coverage * Minimal (C = n + 4) * Universal * Regular Patterns * Linear increase

7. 7 Other Reed-Muller Canonical Forms PPRM (Positive Polarity Reed-Muller) x 1 x 2 x 3  x 1 x 2 FPRM (Fixed Polarity Reed-Muller) x 1 x 2 x ’ 3  x 2 x ’ 3 GRM (Generalized Reed-Muller) x 1  x 2  x ’ 2 x ’ 3 Free Expression ESOP (EXOR-Sum-of-Products) x 1 x 2 x 3  x ’ 1 x ’ 2 x ’ 3 PPRM FPRM GRM ESOP Introduction

8. 8 Comparison of the Number of Product Terms: Introduction

9. 9 * Perfect for BIST ! Testing Two-level AND-EXOR Networks * 100% single stuck at faults * Minimal C = n + 6 * Universal * Regular * Linear size increase

10. 10 much shorter test cycle than pseudo-random and pseudo- exhaustive test sets better fault coverage than a pseudo-random test set no test point insertion required a fixed, simple, and easily expandable pattern generator Testing Two-level AND-EXOR Networks Advantages of deterministic testing for ESOP

11. 11 ESOP Deterministic Pattern Generator Testing Two-level AND-EXOR Networks PRPG Circuit Under Test MISR EDPG Easily Testable 2-level ESOP Network Built-in Self-Test Circuitry for ESOP Networks

12. 12 ESOP Deterministic Pattern Generator Testing Two-level AND-EXOR Networks Linearly expandable No initialization seed & circuitry Much shorter cycle than a PRPG Comparable size to PRPG (see later)

13. 13 FSM (Part II) for EDPG Testing Two-level AND-EXOR Networks

14. 14 Comparisons of the number of test vectors for 100% single stuck- at fault fault coverage Testing Two-level AND-EXOR Networks Experimental Results

15. 15 Comparisons of the number of test vectors for 100% single stuck- at fault fault coverage (cont…) Testing Two-level AND-EXOR Networks

16. 16 Area and delay comparisons (LSI Logic Corp., 0.5 micron) Testing Two-level AND-EXOR Networks

17. 17 Area comparisons (Cont...) Testing Two-level AND-EXOR Networks

18. 18 Multiple Fault Simulation Results Testing Two-level AND-EXOR Networks

19. 19 Testing Multi-level AND-EXOR Networks Two-level implementations –easily testable –large delay It is possible to factorize the two-level ESOP expression Universal testing of two-level ESOPs can be adopted for multi-level testing –requires scan registers

20. 20 Testing Multi-level AND-EXOR Networks Example: The multi-output function, X = acefg  ace’f’g’  ad’efg  ad’e’f’g’  ajh’i  ajd  b’cefg  b’ce’f’g’  b’d’efg  b’d’e’f’g’  b’h’ij  bdj Y = bg’  a’cefg  a’d’efg Z = adj  b’dj  ah’ij  b’h’ij can be factorized as, X = U[V(efg  e’f’g’)  jW] Y = bg’  a’efgV Z = jUW where, U = a  b’ V = c  d’ W = h’i  d

21. 21 Implementation without testability improvements Testing Multi-level AND-EXOR Networks

22. 22 Inserting Literal Part Testing Multi-level AND-EXOR Networks

23. 23 Inserting Check Part Testing Multi-level AND-EXOR Networks

24. 24 Creating cascade of EXOR gates at each level Testing Multi-level AND-EXOR Networks

25. 25 Identifying ESOP Planes Testing Multi-level AND-EXOR Networks

26. 26 Inserting specialized Scan Registers and Scan Path Testing Multi-level AND-EXOR Networks

27. 27 TESTING SCHEME: Each level is tested separately (can be improved) ESOP planes of the same level are tested in parallel Test vectors of the first level are applied from the primary inputs in parallel Test vectors of the internal levels are applied from the primary inputs and from the scan registers The bits applied from the scan registers are shifted into the scan path before applied in parallel The network results are collected by the scan registers and shifted out, and/or observed from the primary outputs Testing Two-level AND-EXOR Networks

28. 28 Implementation of Scan Registers Testing Multi-level AND-EXOR Networks In normal circuit operation, only one mux delay added Inserted only at the output of internal ESOP planes

29. 29 Scan Register mode of operations Testing Multi-level AND-EXOR Networks

30. 30 Scan Register mode of operations Testing Multi-level AND-EXOR Networks

31. 31 Scan Register mode of operations Testing Multi-level AND-EXOR Networks

32. 32 Critical Path Delay = 2.95 ns Testing Multi-level AND-EXOR Networks vs. 4.33 ns of 2-level impl.

33. 33 Testing Multi-level AND-EXOR Networks (4 AND3 + 5 AND2 + 24 EXOR2) gates + 5 SR vs. (17 AND3 + 24 AND2 + 33 EXOR2) gates of 2-level impl.

34. 34 Future Directions Developing a universal test set for bridging and stuck- open faults Developing a factorization/decomposition method targeting EXOR-based multi-level synthesis and universal (deterministic) testability

35. 35 Advantages and Disadvantages of the New Scheme Test set is exponentially smaller than a pseudorandom test set and much smaller than algorithmically generated test set for 100% coverage of single stuck-at faults Properties of deterministic pattern generator for BIST –easy to implement (small area overhead) –does not require seed generation –guarantees 100% testability Detects significant fraction of multiple stuck-at faults and bridging faults Cascade of EXOR gates is relatively slow Area of the AND-EXOR circuit is relatively large ESOP factorization algorithm is computationally complex

36. 36 Rereferences [1] Ugur Kalay, Douglas V. Hall, Marek A. Perkowski. “A Minimal Universal Test Set for Self-Test of EXOR-Sum-of- Products Circuits”. IEEE Trans. Comp. Vol. 49, N3, March 1999, pp.267-276. [2] Ugur Kalay, Marek Perkowski. “Rectangle Covering Factorization of EXORs into Scan-Based Levelized Circuits with Universal Test Set”. Proc. of International Workshop on Application of Reed-Muller Expansion in Circuit Design. 1999.