1. Team W1 Design Manager: Rebecca Miller 1. Bobby Colyer (W11) 2. Jeffrey Kuo (W12) 3. Myron Kwai (W13) 4. Shirlene Lim (W14) Stage II: February 4 th 2004 SIZE ESTIMATES/FLOORPLAN Presentation #3: Rijndael Encryption Overall Project Objective: Implement the new AES Rijndael algorithm on chip 18-525 Integrated Circuit Design Project

2. Status  Design Proposal  Architecture Proposal  Size Estimates/Floorplan  Pipelined Structural Verilog (done)  More accurate Transistor counts  Floorplan  More accurate area estimates  Block density  Local vs Global Interconnect Layers  Metal Directionality  To be Done  Schematic Design (70% done)  Layout (10% done)  Simulations/Optimizations  Everything else… 18-525 Integrated Circuit Design Project

3. Design Decisions PREVIOUS PROBLEMS Timing Issues Clock skew Pipelined Design Research on clock tree implementations  DECISIONS  Pipelined Design  Process Key Schedule first then the encryption of plain text  Clock will be in the form of clock tree, shaped like a menorah  Will buffer more to minimize clock skew 18-525 Integrated Circuit Design Project

4. Behavioral Verilog Results 18-525 Integrated Circuit Design Project

5. Structural Verilog Results

6. Algorithm Description 18-525 Integrated Circuit Design Project AddRoundKey ByteSubShiftRowMixColumnKeyAdd ByteSubShiftRowKeyAdd Cipher Key Plain Text Round Key Cipher Text RoundKey FINAL ROUND REPEAT 9 ROUNDS INITIAL ROUND

7. Top Level 18-525 Integrated Circuit Design Project

8. Top Level

9. MixColumn

10. XTime 18-525 Integrated Circuit Design Project

11. RoundPermutation

12. Final Text Output

13. 18-525 Integrated Circuit Design Project COMPONENTS AREA ESTIMATE ( um 2 ) Key Schedule  Registers & XORs 351 um x 70 um = 24,570 um 2 ROM  SBOX (2) 50 um x 170 um x 2 = 14,000 um 2  Control Logic (352 um x 70 um) – 14,000 um 2 = 10,640 um 2 Transformation  Register & XORs 160 um x 352 um = 56,320 um 2 Others  Buffers & Wiring 10% = 10,553 um 2 TOTAL 116,083 um 2 (~350 um x ~350 um) AREA ESTIMATE

15. Metal Directionality

16. Block Density 18-525 Integrated Circuit Design Project Area = 116,083 um 2 Transistors = 26,250 Density = ~0.23 transistors/um 2

17. Original Transistor Count (Assuming 32-bit Implementation)  ~256 Registers~3500  XORs~1200  Inverters/Buffers~500  SBOX  Registers~12000  Key Schedule  XORs~100  Shifters (Hardcoded – Just routing wires) 0  Muxes~8000 Total:~25300 18-525 Integrated Circuit Design Project

18. Previous Transistor Count (Assuming 32-bit Implementation)  SBOX – Part of ROM (2)~4000  Control Logic (2)~4000  Multiplier(20)~12000  Adders (10)~2500  RCON – Part of ROM (1)~1000  Buffering/MUXes~2000  XORs~5000 Total:~30500 18-525 Integrated Circuit Design Project

19. New Transistor Count (Assuming 32-bit Implementation)  XORs14,336  DFFs6,416  ANDs 120  SBOX2304  Muxes & Demuxes1074  Buffers (10%)2000 Total: 26,250 18-525 Integrated Circuit Design Project

20. Problems  Need to run simulations on schematic to decide clock divider implementation  Not enough time in a day…

21. Questions? 18-525 Integrated Circuit Design Project