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1 Lecture 4: Transistor Summary/Inverter Analysis Subthreshold MOSFET currents IEEE Spectrum, 7/99, p. 26.

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Presentation on theme: "1 Lecture 4: Transistor Summary/Inverter Analysis Subthreshold MOSFET currents IEEE Spectrum, 7/99, p. 26."— Presentation transcript:

1 1 Lecture 4: Transistor Summary/Inverter Analysis Subthreshold MOSFET currents IEEE Spectrum, 7/99, p. 26

2 2 Lecture 4: Transistor Summary/Inverter Analysis I D versus V DS -4 V DS (V) 00.511.522.5 0 0.5 1 1.5 2 2.5 x 10 I D (A) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V 00.511.522.5 0 1 2 3 4 5 6 x 10 -4 V DS (V) I D (A) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V ResistiveSaturation V DS = V GS - V T Long ChannelShort Channel © Digital Integrated Circuits 2nd

3 3 Lecture 4: Transistor Summary/Inverter Analysis Current-Voltage Relations in the Deep-Submicron Era Linear Relationship -4 V DS (V) 00.511.533.3 0 0.5 1 1.5 2 2.5 x 10 I D (A) VGS= 3.3 V VGS= 2.5 V VGS= 1.65 V VGS= 1.0 V nFET 2.5

4 4 Lecture 4: Transistor Summary/Inverter Analysis Current-Voltage Relations in the Deep-Submicron Era Linear Relationship VGS= -3.3 V VGS= -2.5 V VGS= -1.65 V VGS= -1.0 V -4 0 -0.5 -1.5 -2 -2.5 x 10 I D (A) 0 V DS (V) -0.5 -1.5 -3.0 -3.3 -2.5 pFET

5 -4 V DS (V) 00.511.533.3 0 0.5 1 1.5 2 2.5 x 10 I D (A) VGS= 3.3 V VGS= 2.5 V VGS= 1.65 V VGS= 1.0 V 2.5

6 VGS= -3.3 V VGS= -2.5 V VGS= -1.65 V VGS= -1.0 V V DS (V) -0.5 -1.5 -3.0-3.3 -4 0 -0.5 -1.5 -2 -2.5 x 10 I D (A) 0 -2.5

7 7 Lecture 4: Transistor Summary/Inverter Analysis W/L and transistor sizing

8 VGS= -3.3 V VGS= -2.5 V VGS= -1.65 V VGS= -1.0 V -4 0 -0.5 -1.5 -2 -2.5 x 10 I D (A) 0 V DS (V) -0.5 -1.5 -3.0-3.3 -2.5

9 9 Lecture 4: Transistor Summary/Inverter Analysis Inverter layout

10 10 Lecture 4: Transistor Summary/Inverter Analysis Some Definitions V oh  output voltage high V ol  output voltage low V ih  minimum allowed voltage input for a logic-low output V il  maximum allowed voltage input for a logic-high output Noise margin: NM L = V il – V ol NM H = V oh – V ih V m  switching threshold (where V out =V in ) Fan-in: The number of inputs to a gate Fan-out: The number of loads (min geometry) the gate drives Propagation delay: The signal delay through a gate (50% points of input and output) Rise and fall times: Time for a signal to transition from 10% to 90% of its logic swing Power–delay product (gate power)×(gate prop delay)

11 11 Lecture 4: Transistor Summary/Inverter Analysis  n /  p ratio (k n /k p ) F V inv is set by  n /  p íYou can size the transistors to place V inv where you want it ç Affects noise margin and speed ç Optimal noise margin: Make p FET wider than n FET

12 12 Lecture 4: Transistor Summary/Inverter Analysis Switching Threshold as a function of Transistor Ratio 10 0 1 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 M V (V) W p /W n © Digital Integrated Circuits 2nd

13 13 Lecture 4: Transistor Summary/Inverter Analysis Inverter power dissipation F Static power íDissipation when the inverter isn’t switching íPrimarily subthreshold currents ç And very small noise currents

14 14 Lecture 4: Transistor Summary/Inverter Analysis Inverter power dissipation (con’t) F Dynamic power: Direct-path current ípFET and nFET are both on during switching ç Direct current path from V dd to gnd íIntegrate curve to find energy loss E direct ç Dissipation = E direct × switching frequency

15 15 Lecture 4: Transistor Summary/Inverter Analysis Inverter power dissipation (con’t) F Dynamic power: Driving load capacitance íCharge capacitor to V dd ; then discharge to gnd íDissipation = CV dd 2 × switching frequency

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