1. 1 Answers to Test 1, Question 1 The functions determines if a positive number is prime. It does this by checking if the number is lower than 4, if so it is prime. It then divides the number by all numbers smaller than n/2. int prime(int n){ int i=2; if(n < 4) return 0; while(i<=n/2){ if(n%i == 0) return 1; i++; } return 0; }

2. 2 Question 2 b 0 4 Result Operation a 2 CarryIn CarryOut 1 3 b 0 4 Result Operation a 2 CarryIn CarryOut 1 3

3. 3 Question 3 ET A = 135M * 3.1 * 2ns = 837M ns = 0.837 sec ET B = 125M *3.2 *(1/450M)ns = 888M ns = 0.888 s A is faster than B by 6% (888/837) Computer A: FE=1.00 (all the instructions are effected), SE = 135/127 = 1.06. (1.00/1.06 + 1 -1)*0.837 = 0.789 sec Computer B: FE=0.25, SE=3.2/2.6 = 1.23 (0.60/1.23 + 0.40)*0.888 = 0.788 sec Now B is faster than A by 0.1%

4. 4 Question 4 Mapping an address into a cache is done by: 1. Computing the block address of the address. Dividing the address into the number of words in each block. 2. Finding the cache location by computing the block address modulo (%) the number of blocks in the cache. 3. The offset of the word in the block, is the remainder of step 1. To get the block address of each address we have to divide by the number of words in the block, which is 1. This number modulo 16 is the cache block the address is mapped to. The only hits are the last accesses to 5, 9, and 17. All the other accesses are misses, so the hit rate is 19%.

5. 5 Question 4 (cont) If the block size is 4 we must divide each address by 4 to get the block address and then compute modulo 4. Now we have 1(m), 4(m), 8(m), 5(h), 20(m), 17(m), 19(h), 56(m), 9(m), 11(h), 4(m), 43(m), 5(h), 6(h), 9(m), 17(h). The hit rate is now 37%. For the 3 rd case the mapping is set address modulo number of sets. So each address has to be divided by 8 and then modulo 2 taken: 1(m), 4(m), 8(m), 5(h), 20(m), 17(m), 19(h), 56(m), 9(h), 11(h), 4(m), 43(m), 5(h), 6(h), 9(h), 17(h). The hit ratio is now 50%.

6. 6 Question 5 If the loop body is less than 131064 bytes a bne can be used: bne $a0,$a1,End … End: If the loop body is larger than 131064 bytes a j must be used: beq $a0,$a1,L1 j End L1: … End:

7. 7 Question 5 (cont) If the loop spans a 256MB boundary j can't be used. Only jr can be used. The problem is getting the address in a register. Using lui or a shift operation can solve the problem: lui $t0,0xFF30 # li $t0,0xFF30 # sll $t0,$t0,16 addi $t0,$t0,0x800 beq $a0,$a1,L1 jr $t0 L1: … End:

8. 8 Question 6 AMAT = 0.90*2 + 0.1(0.90*6 + 0.1*13) = 2.47 widening the bus between memory to L2 can cut down the miss penalty, as we can transfer more data per cycle. On the other hand more bus lines are needed which can be expensive. Longer blocks in L2 can take advantage of spatial locality and raise the hit-ratio. On the other hand not the whole block may be used. It also might effect the miss penalty as more data has to be brought from main memory. Going to direct mapped might reduce the hit-time, but might reduce the hit-ratio as well.

9. 9 Question 6 (cont) Let's assume that widening the bus reduces the miss penalty to 10 cycles: AMAT = 0.90*2 + 0.1(0.90*6 + 0.1*10) = 2.44 Let's assume that raising the L2 block size raises the hit-ratio to 0.95, but also raises the miss penalty to 15 cycles. AMAT = 0.90*2 + 0.1(0.95*6 + 0.05*15) = 2.445 Let's assume that going from 4-way set associative to direct-mapped, reduces the hit time to 1 cycle and the hit ratio to 80%. AMAT = 0.80*1 + 0.2(0.90*6 + 0.1*13) = 2.14

10. 10 Question 7 swap: lw $t0,0($a0)# temp = *a lw $t1,0($a1)# $t1 = *b sw $t1,0($a0) # *a = *b sw $t0,0($a1) # *b = temp jr $ra # return

11. 11 Question 8 What is reduced is the number of bits for the opcode, this reduces the number of possible instructions. RISC processors have instructions that are the same length (1 word) as opposed to GPRs that have variable length instructions. RISC processors have 3 operand instructions as opposed to 2 operand instructions. RISC processors access memory only through Load/Store instructions, as opposed to GPRs where all instructions (even ALU instructions) can have memory operands. RISC programs might have more instructions.