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Uli Schäfer JEM1 In input modules T,S probably mix of φ-bins 5,6 due to routing problems of high-speed LVDS links With current algorithm rounding errors.

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Presentation on theme: "Uli Schäfer JEM1 In input modules T,S probably mix of φ-bins 5,6 due to routing problems of high-speed LVDS links With current algorithm rounding errors."— Presentation transcript:

1 Uli Schäfer JEM1 In input modules T,S probably mix of φ-bins 5,6 due to routing problems of high-speed LVDS links With current algorithm rounding errors will lead to dependency of the response on channel mapping…  Modify algorithm

2 Uli Schäfer Algorithms (RTDP) Minor modifications to energy sum algorithm due to re-partitioning on JEM1: Receive energies 4×8 ×(e/h) plus overlap (total 88 ch.) Synchronisation, parity, mask Generate jet elements E T =E e +E h, Saturate jet elements at 1 TeV, send to jet processor @80Mb/s, 5- bit wide From jet elements calculate E X and E Y by multiplying cosφ, sinφ (accuracy: 10bit E T ×12-bit coefficient -> 12-bit (.25 GeV resolution)) Threshold (E X,E Y ), E T Pre-sum E X, E Y and E T : 12 jet elements (JEM0:4) Truncate to 1GeV resolution Saturate at 4 TeV Send to sum processor @ 40Mb/s (JEM0:80Mb/s) : 12&14&14 bit Final summation over 3 partial sums (JEM0:8) Truncate to 1GeV resolution Quad-linear encoding of energies (8 bit, 4 TeV range) Saturation (4TeV) Parity

3 Uli Schäfer H/W Status & Plans Status MZ / HD joint tests on Dec. 10: Analogue signals successfully sent through PPr and JEM, captured in spy memories. RAL remote JEM/ROD test on Dec. 16 (to be continued). No success so far, G-link /DAV received on ROD though no data sent  After installation of new Cadence release, JEM1 design progressing well. Hope to have the PCB design ready for submission ~Jan. 6/7 PCB and assembly : order out (~16.8 K€) Plans: Continue Mainz tests of energy and integrated (J/E) algorithms. Jitter tests / track down G-link problems another RAL test ~ Jan 13 –ROD Set up stand-alone test bench for input processors (  Andrey) to have well-tested daughter modules when JEM1 arrives Keep JEM0s up and running through first stage of slice test


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