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An Automatic AMBA Wrapper Generation Tool for Embedded Cores Laboratory for Reliable Computing (LaRC) Electrical Engineering Department National Tsing.

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Presentation on theme: "An Automatic AMBA Wrapper Generation Tool for Embedded Cores Laboratory for Reliable Computing (LaRC) Electrical Engineering Department National Tsing."— Presentation transcript:

1 An Automatic AMBA Wrapper Generation Tool for Embedded Cores Laboratory for Reliable Computing (LaRC) Electrical Engineering Department National Tsing Hua University

2 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 2 OutlineOutline  Introduction  Template and Configuration  Verification and Simulation Result  Conclusion

3 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 3 OutlineOutline  Introduction  AMBA System  AMBA Wrapper Generation Tool  Template and Configuration  Verification and Simulation Result  Conclusion

4 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 4 AMBA System  Advanced Microcontroller Bus Architecture  Distinct Buses Defined within AMBA  Advanced High-performance Bus (AHB)  Advanced System Bus (ASB)  Advanced Peripheral Bus (APB)

5 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 5 AMBA System

6 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 6 AHB Model Diagram

7 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 7 AHB Multiplexer Scheme

8 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 8 AHB Basic Transfer Cycles

9 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 9 Overview of AHB Wrapper Generation Tool

10 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 10 The Flow to Use Tool

11 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 11 Software System

12 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 12 OutlineOutline  Introduction  Template and Configuration  AHB Slave  AHB Master  Verification and Simulation Result  Conclusion

13 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 13 AHB Slave Template Interface  Define some established signals for user to choose.

14 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 14 AHB Slave Template  WR_valid: this is a signal from Wrapper to slave IP core. Its function is to indicate that write data is valid or not.  WR_valid: connected_port_name,, time_offset  WR_valid: wr_valid, high, 1 Without WR_ready With WR_ready

15 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 15 AHB Slave Template  RD_valid: this is a signal from Wrapper to slave IP core. Its function is to indicate that Wrapper will read data from slave, that is, Wrapper is ready to be transferred data from slave.  RD_valid: connected_port_name,, time_offset  RD_valid: rd_valid, high, 1 Wrapper Without RD_ready Wrapper With RD_ready

16 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 16 AHB Slave Template  Range[N-1:0]: this is a signal from Wrapper to slave IP core. Its function is to decode address and activate some signal high or low. And ‘ N ’ is an arbitrarily positive integer.  Range: [, range_number, {connected_port_name, address_mask_pattern,, delay}]  Range: Yes, 2, dec_out1, 8000_xxxx, high, 0, dec_out2, 8100_xxxx, low, 1

17 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 17 AHB Slave Template  Start_WR: Its function is to indicate that an AHB master writes the first transfer of a burst.  End_WR: Its function is to indicate that an AHB master writes the last transfer of a burst.  Start_WR: [, connected_port_name, start_address,, time_offset]  Start_WR: Yes, init, 0, high, 0  End_WR: [, connected_port_name, start_address,, time_offset]  End_WR: Yes, last, 0, high, 0

18 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 18 AHB Slave Template  Chip_select: this is a signal from Wrapper to slave IP core. Its function is to enable the slave core. It ’ s timing can be specified by time offset with respect to the reference cycle.  Chip_select: [, connected_port_name,, time_offset]  Chip_select: yes, cen, low, 1

19 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 19 AHB Slave Template  WR_Addr: this is a signal from Wrapper to slave IP core. Its function is to translate AHB address to IP core or to translate IP address to AHB.  WR_Addr: connected_port_name, bit_width, mask_pattern, time_offset  WR_Addr: waddr_porta, 16, 0000_ffff, 1  WR_Data: this is a signal from Wrapper to slave IP core. It carries write data from Wrapper to IP core. It is allowed that there are several write data ports.  WR_data: connected_port_name, bit_width, time_offset, address_mask_pattern  WR_data: wdata_porta, 32, 1, 6000_xxxx  RD_Data: this is a signal from slave IP core to Wrapper. It carries read data from IP core to Wrapper. It is allowed that there are several read data ports.  RD_data: connected_port_name, bit_width, address_mask_pattern  RD_data: rdata_porta, 32, 6100_xxxx

20 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 20 AHB Slave Template Example Range: Yes, 2, dec_out1, 8000_xxxx, high, 0, dec_out2, 8100_xxxx, low, 1 WR_valid: wr_valid, high, 1 RD_valid: rd_valid, high, 1 WR_Addr: address, 16, 0000_ffff, 1 WR_data: data_a, 32, 1, 6000_xxx WR_data: data_b, 16, 1, 6001_xxx RD_data: status, 32, 6100_xxx Range: Yes, 2, dec_out1, 8000_xxxx, high, 0, dec_out2, 8100_xxxx, low, 1 WR_valid: wr_valid, high, 1 RD_valid: rd_valid, high, 1 WR_Addr: address, 16, 0000_ffff, 1 WR_data: data_a, 32, 1, 6000_xxx WR_data: data_b, 16, 1, 6001_xxx RD_data: status, 32, 6100_xxx

21 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 21 AHB Master Template

22 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 22 Write Transactions of AHB Master Wrapper

23 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 23 Read Transactions of AHB Master Wrapper

24 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 24 OutlineOutline  Introduction  Template and Configuration  Verification and Simulation Result  AHB Slave Wrapper  For Template Protocol  For AMBA Compliance  AHB Master Wrapper  For Template Protocol  For AMBA Compliance  Conclusion

25 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 25 EASY (Example AMBA SYstem)

26 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 26 Verification of WR_valid, RD_valid, Chip_select, WR_data, RD_data and WR_addr  32 sequence address (HADDR)  0xE0000200  0xE0000204  0xE0000208  0xE000027C  5 wrapper type  5 types of timing-shift … …

27 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 27 Verification of AHB Slave Wrapper  Simulation with a counter and a SRAM

28 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 28 Verification of Range Signal  Range  0xE1000000, 0xE1000004, 0xE1000008, 0xE100000C, 0xE1000010  5 wrapper type: total pattern number is 25

29 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 29 Verification of Start_WR and End_WR Signals  Start_WR  0xE2000000  HBURST[2:0] = 3’b001 (Incrementing Burst)  5 wrapper type: total pattern number is 5  End_WR  0xE3000000  HBURST[2:0] = 3’b001 (Incrementing Burst)  5 wrapper type: total pattern number is 5

30 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 30 AMBA-Compliant Verification for AHB Slave

31 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 31  Basic transfers  Transfers to Other Slaves  0, 1 and greater than 1 wait state  An ERROR response  A RETRY response  Basic Read transfer with Wait States  Read transfers with IDLE cycles  Read transfers with BUSY cycles  Basic Write transfer with Wait States  Write transfers with IDLE cycles  Write transfers with BUSY cycles Testbench Requirements for a Slave Interface

32 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 32 Testbench Requirements for a Slave Interface  Basic Burst transfers  Error response

33 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 33 Verification Architecture of AHB Master Wrapper

34 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 34 Testbench to Verify AHB Master Wrapper  For write/read data  cmd_valid = 1  command: ADDRESS = 0x0~0x1F  (cmd_latched)  wdata_valid = 1  (wdata_latched)  cmd_valid = 1  command: ADDRESS = 0x0~0x1F  (cmd_latched)  rdata_valid = 1  (rwdata_latched)

35 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 35 Testbench to Verify AHB Master Wrapper  For response  cmd_valid = 1  command: ADDRESS = 0xA0~0xA2  (resp_valid)  resp_latched = 1  Check response  Also check the operation of MERROR, MREADY and MRETRY  Drive MADDR, MWRITE, MTRANS, MBUSREQ and MBURST respectively and then check the behavior of AHB

36 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 36 AMBA-Compliant Verification for AHB Master

37 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 37 Testbench Requirements for a Master Interface  First Transfer Responses  Ensure that all types of response are seen to the first transfer of burst.  Middle Transfer Responses  Last Transfer Responses  Losing Bus Ownership  Grant Response Combinations  Retry Responses  Multi-cycle Responses  ERROR, RETRY and SPLIT with more than two cycles  Busy Transfers  Generate a BUSY transfer for all responses to the previous transfer

38 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 38 Experiment for IPs  Compare the time of the two flow to produce AHB wrapper

39 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 39 Experiment Results AESRSA1RSA2HMAC Total Time (Manual) 3-day3~4 days7-day Total Time (Generator) 12 min.23 min.9 min.20 min. Manual Area (gates) 22132627394 Generator’s Area (gates) 257419341108 Area Overhead 16.29%28.53%24.91%16.40%

40 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 40 OutlineOutline  Introduction  Definition of Template Signals  Definition of Configuration  Simulation and Result  Conclusion

41 Laboratory for Reliable Computing (LaRC)May-2004 Ming-Shen Liu & Cheng-Wen Wu 41 ConclusionConclusion  The method provides a simple and direct way that designers’ IP core can be attached onto the AHB.  Advantage of using Wrapper Generator:  Reducing time of producing wrapper:  Producing manually: hours  Producing by Generator: minutes  Reducing the opportunity of wrapper’s error:  Disadvantage of using Wrapper Generator:  Area overhead  Can’t support every design type

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