1. Group M3 Nick Marwaha Craig LeVan Jacob Thomas Darren Shultz Project Manager: Zachary Menegakis February 28, 2005 MILESTONE 7 Component Layout DSP 'Swiss Army Knife' Overall Project Objective: General Purpose Digital Signal Processing Chip

2. STATUS Design Proposal (Done) Architecture (Done) Size Estimates/Floorplan/Verilog (95%) Gate Level Design (99%) Component Layout (Done) Functional Block (50%) To Be Done Complete layout of functional blocks Wallace Tree Multiplier, etc. Layout of Adder and div remain Schematic Make remaining adjustments for comb/Wallace Top-level Verification Test adjusted blocks

3. DESIGN DECISIONS Layout Re-did XOR and FA (and others) using M2 to reduce size Going to need all four layers for the fp_mult Not a big issue because we don’t route over them Wallace Tree Multiplier Fully implemented booth encoding All blocks for wallace tree done to conform to aspect ratio

4. MENTAL BREAK

5. OLD WALLACE TREE

6. NEW WALLACE TREE

7. Wallace Tree Mult

8. Booth Encoding – PP_Gen

9. TRANSISTOR COUNT

10. LAYOUT UPDATE - FA

11. LAYOUT UPDATE REG BOOTH DECODER

12. LAYOUT UPDATE 3:2 COMPRESSOR COMPARATOR

13. FLOORPLAN BEFORE

14. FLOORPLAN AFTER

15. UPDATE – TEXT VERSION Since Wednesday @ 3pm: Craig – Worked on Booth Recoding and floorplan Darren – Got in a car… Jake – Worked on layout (only 13hrs straight this time) Nick – ditto

16. PROBLEMS & QUESTIONS Booth Recoding Still walking through Problem: Timing issues with top level design. Haven’t tackled yet (fixing lower blocks to avoid complications*) Problem: Spring break We want one * scientific method: only test one variable at a time