Download presentation
Presentation is loading. Please wait.
1
Modern VLSI Design 2e: Chapter 6 Copyright 1998 Prentice Hall PTR Topics n Memories: –ROM; –SRAM; –DRAM. n PLAs.
2
Modern VLSI Design 2e: Chapter 6 Copyright 1998 Prentice Hall PTR High-density memory architecture
3
Modern VLSI Design 2e: Chapter 6 Copyright 1998 Prentice Hall PTR Memory operation n Address is divided into row, column. –Row may contain full word or more than one word. n Selected row drives/senses bit lines in columns. n Amplifiers/drivers read/write bit lines.
4
Modern VLSI Design 2e: Chapter 6 Copyright 1998 Prentice Hall PTR Read-only memory (ROM) n ROM core is organized as NOR gates - pulldown transistors of NOR determine programming. n Erasable ROMs require special processing that is not typically available. n ROMs on digital ICs are generally mask- programmed - placement of pulldowns determines ROM contents.
5
Modern VLSI Design 2e: Chapter 6 Copyright 1998 Prentice Hall PTR ROM core circuit
6
Modern VLSI Design 2e: Chapter 6 Copyright 1998 Prentice Hall PTR Static RAM (SRAM) n Core cell uses six-transistor circuit to store value. n Value is stored symmetrically - both true and complement are stored on cross- coupled transistors. n SRAM retains value as long as power is applied to circuit.
7
Modern VLSI Design 2e: Chapter 6 Copyright 1998 Prentice Hall PTR SRAM core cell
8
Modern VLSI Design 2e: Chapter 6 Copyright 1998 Prentice Hall PTR SRAM core operation n Read: –precharge bit and bit’ high; –set select line high from row decoder; –one bit line will be pulled down. n Write: –set bit/bit’ to desired (complementary) values; –set select line high; –drive on bit lines will flip state if necessary.
9
Modern VLSI Design 2e: Chapter 6 Copyright 1998 Prentice Hall PTR SRAM sense amp
10
Modern VLSI Design 2e: Chapter 6 Copyright 1998 Prentice Hall PTR Sense amp operation n Differential pair - takes advantage of complementarity of bit lines. n When one bit line goes low, that arm of diff pair reduces its current, causing compensating increase in current in other arm. n Sense amp can be cross-coupled to increase speed.
11
Modern VLSI Design 2e: Chapter 6 Copyright 1998 Prentice Hall PTR 3-transistor dynamic RAM (DRAM) n First form of DRAM - modern commercial DRAMs use one-transistor cell. n 3-transistor cell can easily be made with a digital process. n Dynamic RAM loses value due to charge leakage - must be refreshed.
12
Modern VLSI Design 2e: Chapter 6 Copyright 1998 Prentice Hall PTR 3-T DRAM core cell
13
Modern VLSI Design 2e: Chapter 6 Copyright 1998 Prentice Hall PTR 3-T DRAM operation n Value is stored on gate capacitance of t 1. n Read: –read = 1, write = 0, read_data’ is precharged; –t 1 will pull down read_data’ if 1 is stored. n Write: –read = 0, write = 1, write_data = value; –guard transistor writes value onto gate capacitance.
14
Modern VLSI Design 2e: Chapter 6 Copyright 1998 Prentice Hall PTR 1-transistor dynamic RAM (DRAM) n Modern commercial DRAMs use one- transistor cell. n One-transistor/one-capacitor : the charge is stored on a pure capacitor. n Two major techniques for DRAM fabrication : stacked capacitor and trench capacitor.
15
Modern VLSI Design 2e: Chapter 6 Copyright 1998 Prentice Hall PTR 1-T DRAM core cell word bit
16
Modern VLSI Design 2e: Chapter 6 Copyright 1998 Prentice Hall PTR 1-T DRAM operation n Read: –bit line is precharged before word is activated; –if 0 is stored, charge will flow from the bit line to the capacitor (destructive). –A sense amp can be used to detect the dip in voltage n Write: –the bit line is set and the capacitance is forced.
17
Modern VLSI Design 2e: Chapter 6 Copyright 1998 Prentice Hall PTR Programmable logic array (PLA) n Used to implement specialized logic functions. n A PLA decodes only some addresses (input values); a ROM decodes all addresses. n PLA not as common in CMOS as in nMOS, but is used for some logic functions.
18
Modern VLSI Design 2e: Chapter 6 Copyright 1998 Prentice Hall PTR
19
Modern VLSI Design 2e: Chapter 6 Copyright 1998 Prentice Hall PTR PLA structure n AND plane, OR plane, inverters together form complete two-level logic functions. n Both AND and OR planes are implemented as NOR circuits. n Pulldown transistors form programming/personality of PLA. Transistors may be referred to as programming tabs.
20
Modern VLSI Design 2e: Chapter 6 Copyright 1998 Prentice Hall PTR PLA AND/OR cell programming tab no tab V SS input 1input 2 output 1 output 2
Similar presentations
© 2025 SlidePlayer.com. Inc.
All rights reserved.