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Interconnect Implications of Growth-Based Structural Models for VLSI Circuits* Chung-Kuan Cheng, Andrew B. Kahng and Bao Liu UC San Diego CSE Dept. e-mail: {kuan,abk,bliu}@cs.ucsd.edu *Supported by a grant from Cadence Design Systems, Inc. and by the MARCO Gigascale Silicon Research Center.
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Presentation Outline Introduction and Motivation Random Growth Models Experiments Conclusion and Future Work
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VLSI circuits: degree d == # adjacent gates P(d) == # gates with degree d f == # gates being driven N(f) == # nets with fanout f G == # gates T == # terminals E == # crossing edges (connections between two gates on different sides of a partition) Definitions g3 g1 g2 G = 3 E = 6 T = 4 g3 D(g3) = 5 P(3) += 1 P(5) += 1 P(2) += 1 f = 3 N(1) += 2
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VLSI Power-Law Phenomena Rent’s rule Crossing edge scaling T == # terminal, G: # gate, p == Rent exponent E == # connections between two gates on different sides of the partition
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VLSI Power-Law Phenomena (cont.) Vertex degree Net fanout P(d) == # vertices with degree d d == vertex degree N(f) == # nets with fanout f f == net fanout
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Power-Law Phenomena in other Contexts Zief’s law English word frequency with rank i is proportional to i - Lotka’s law (Yule’s law) # authors (# papers) -2 Power-law vertex degree distribution WWW (in-degree exponent 2.1, out-degree 2.45) actor connectivity (exponent 2.3) paper citation (exponent 3) power grid (exponent 4)
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Rent’s Rule Based VLSI Models Claims that Rent’s rule implies fanout distribution Zarkesh-Ha: Stroobandt-Kurdahi: logistic equations Are they really correlated? Rent p depends on partitioning method, fanout distribution does not Families of topologies with different p and identical N(f) 1-D mesh: p = 0, N(1) = # nets, N(f 1) = 0 2-D mesh: p = 0.5, N(1) = # nets, N(f 1) = 0 3-D mesh: p = 0.667, N(1) = # nets, N(f 1) = 0 Our experiments fail to confirm the p-3 fanout exponent
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Our Motivation Open problems what are the reasons behind all these power-law scaling phenomena? what are the relations between these power-law scaling phenomena? Are they correlated? Our aim to better understand scaling phenomena and structural properties in VLSI circuits eventually, to better estimate VLSI interconnect parameters
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Presentation Outline Introduction and Motivation Random Growth Models Experiments Conclusion and Future Work
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Random Growth Model (Framework) Random growth in time n 0 primary vertices at timestep 0 1 new vertex with m edges to existing vertices, added at each time step Preferential attachment (Barabasi, Kumar, Pref, Temp 1, Temp 2...) Interpretation as hypergraph Each vertex has m input (backward) edges and 1 output (forward) hyperedge
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Barabasi Model Given: Random growth Preferential attachment Result: Vertex degree
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Kumar Model Given: Random growth of vertices Random link to other vertices with probability Copy links from a random vertex with probability 1- Results: Power-law vertex degree distribution
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New Pref Model Preferential attachment After integration, vertex degree
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New Pref Model Vertex degree probability Probability density d = f + m, so fanout
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New Pref Model Terminal Crossing edge
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New Temporal Models Temporal attachment: Temp 1 (s = 1): attachments that prefer temporal locality Temp 2 (s = 0): random equiprobable attachment to all previous vertices Temp 3 (s = ): extreme temporal locality (a vertex connects only to its temporally immediate neighbors)
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Summary of Models BarabasiPrefTemp 1Temp 2
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Presentation Outline Introduction and Motivation Random Growth Models Experiments Conclusion and Future Work
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Experimental Setting 21 industry standard-cell test cases with between 4K and 283K cells Fanout and vertex degree obtained by scanning netlist files E and T from UCLA Capo placer remove Rent region II data average blocks with same gate number Best-fitted exponents by linear regression Minimum standard deviation fit from non-linear regression (Levenberg-Marquardt variant)
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Experimental Observations Pref model provides most reasonable fanout distribution and vertex degree distribution prediction Barabasi model gives best E prediction Temp 2 model gives best T prediction Case19 183k 181k 1.1e6 1.1e6 5.3e6 1.6e6 1.4e6 4.7e4 6.0e4 4.8e5 4.8e4 Case #cells #nets standard deviation of E standard deviation of T Test Total Total best-fit Bara. Pref Temp 1 Temp 2 best-fit Bara. Temp 1 Temp 2 Case18 182k 181k 1.3e6 1.3e6 4.9e6 1.5e6 1.4e6 3.2e4 4.5e4 2.5e5 3.3e4 Case17 118k 125k 1.4e6 1.5e6 5.4e6 3.1e6 1.4e6 2.4e3 6.5e3 1.8e4 3.8e3 Case16 86k 87k 5.4e5 5.4e5 1.4e6 8.3e5 6.4e5 4.8e3 5.2e3 5.1e4 5.9e3 Case21 283k 285k 1.5e8 1.5e8 1.5e9 1.3e7 4.0e7 2.0e4 3.0e3 9.8e4 2.0e4 Case20 210k 200k 2.2e6 2.2e6 7.3e6 2.4e6 2.3e6 6.6e4 8.0e4 2.7e5 6.7e4
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Experimental Observations ZH does not fit data very well Case21 -1.201 -2.495 5.7e7 6.4e8 Case20 -3.303 -2.405 2.3e8 2.4e8 Case19 -3.983 -2.351 2.5e8 2.8e8 Case18 -4.099 -2.405 2.9e8 3.2e8 Case17 -2.122 -2.644 8.0e7 8.5e7 Case exp. exp. std.dev. std.dev. Test fitted ZH fitted ZH Case16 -2.053 -2.448 2.8e6 3.1e7 N(f) = c 1 (f+c 2 ) q-3 N(f) = c f p-3 N(f) = c (f+m) -3 N(f) = c e -f N(f)
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Experimental Observations Correlation between T and E Correlation between T and N(f) T and E correlated, T and N(f) not correlated
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Experimental Observations Correlation between T and P(d) Correlation between P(d) and N(f) T and P(d), P(d) and N(f) not correlated
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Presentation Outline Introduction and Motivation Random Growth Models Experiments Conclusion and Future Work
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Conclusion Have explored possibility of non-Rent based scaling phenomena in VLSI circuits Proposed new random growth models and studied their implications for VLSI interconnect structure Empirically studied relationships between various interconnect structural characteristics T, E, N(f), P(d)
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Current Work and Open Questions Calculation methodology for confirmation of scaling laws Generation of random netlists that observe multiple scaling laws simultaneously Analytical models with more than one scaling parameter Are these power-law scaling phenomena correlated to each other? Evolution models with copying (“reuse”) Can we have closed-form results? Do evolution models converge or diverge? What are root causes of these scaling phenomena? Design hierarchy? Reuse?
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