1. Chapter 05 Tutorial Using Verilog
Design a 4-bit up-down counter using behavioral level HDL language 1

2. Create a New Project 2

3. Enter a Name and Location for the Project3

4. Create New File 4

5. You can type Verilog on the New File5

6. Example (4位元上下數計數器)
in1
out
in2 s1 6

7. Behavioral level 7

8. Save 8

9. Type “counter.v”
Module name and File name must the same. 9

10. Add Source 10

11. Select “counter.v” 11

12. Select Verilog Design File12

13. Add New Source 13

14. Select Test Bench Waveform14

15. Click OK 15

16. 16

17. Give Input Value 17

18. Save 18

19. Select “View Behavioral..” and Run19

20. See a HDL Test bench 20

21. Select “Generate Expected..” and Run21

22. Result 22

23. Result (cont.) 23

24. Question & Answer