1. Team W1 Design Manager: Rebecca Miller 1. Bobby Colyer (W11) 2. Jeffrey Kuo (W12) 3. Myron Kwai (W13) 4. Shirlene Lim (W14) Stage II: 26 th January 2004 ARCHITECTURE PROPOSAL Presentation #2: Rijndael Encryption Overall Project Objective: Implement the new AES Rijndael algorithm on chip 18-525 Integrated Circuit Design Project

2. Status  Design Proposal  Project Chosen - Alternatives Studied and Eliminated  Verilog Obtained  Architecture Proposal  Final Algorithm Description  Mapping of algorithm to hardware (block diagram)  Behavioral Verilog simulation and test bench  To be Done  Gate Level Design  Schematic Design  Floorplan  Layout  Simulations/Optimizations  Everything else… 18-525 Integrated Circuit Design Project

3. Design Decisions PREVIOUS PROBLEMS Cut down 128-bit design to 32-bit design Different implementations of Rijndael Too many transistors / design too big Parallel design – more transistors but faster?  DECISIONS  Decided/changed 128-bit design to 32-bit design  32-bit design but implementing full SBOX  Decided to stick with the Rijndael implementation that incorporated a multiplier instead of just XORing the values.  Increases complexity of design  Too many transistors/design too big – will further optimize design  Implementation of ROM instead of SRAM or registers  Decided to stick with parallelism  Two different blocks 18-525 Integrated Circuit Design Project

4. Implementation Revised 18-525 Integrated Circuit Design Project Previous Implementation Removed last MixColumn Function Replaced with AddRoundKey in accordance to new implementation chosen

5. Final Algorithm Description 18-525 Integrated Circuit Design Project KeyAdd ByteSubShiftRowMixColumnKeyAdd ByteSubShiftRowKeyAdd Cipher Key Plain Text Round Key Cipher Text RoundKey FINAL ROUND REPEAT 9 ROUNDS INITIAL ROUND

6. Mapping Algorithm to Hardware 18-525 Integrated Circuit Design Project ROM BLOCK New Implementation: 10-stage Pipelined Design  Increased throughput  Increased speed LOOKS SIMPLE BUT… Timing issues… Proposed 2 S-BOX as part of ROM 10 Blocks with 5 Blocks per S-BOX Each Block accessing S-BOX 4 times, total of 20 per S-BOX per clock

7. Block Diagrams (cont’d) 18-525 Integrated Circuit Design Project ROM Control logic Multiplier + ONE “BLOCK” Cipher Key Plain Text RCON

8. FIPS Test Vectors 18-525 Integrated Circuit Design Project Using FIPS Test Vectors for Verilog Simulation Verification  FIPS – Federal Information Processing Standards

9. Verilog Test Bench 18-525 Integrated Circuit Design Project

10. Verilog Simulation (VSim) 18-525 Integrated Circuit Design Project

11. Verification of Output 18-525 Integrated Circuit Design Project

12. Previous Transistor Count (Assuming 32-bit Implementation)  ~256 Registers~3500  XORs~1200  Inverters/Buffers~500  SBOX  Registers~12000  Key Schedule  XORs~100  Shifters (Hardcoded – Just routing wires) 0  Muxes~8000 Total:~25300 18-525 Integrated Circuit Design Project

13. New Transistor Count (Assuming 32-bit Implementation)  SBOX – Part of ROM (2)~4000  Control Logic (2)~4000  Multiplier(20)~12000  Adders (10)~2500  RCON – Part of ROM (1)~1000  Buffering/MUXes~2000  XORs~5000 Total:~30500 18-525 Integrated Circuit Design Project

14. Problems  Timing issues  Clock skew  Pipelined design  Each S-BOX being accessed by several different stages  Research on clock-tree implementations  So we can organize our 10 blocks optimally  Transistor sizing  Transistor sizing affects efficiency of SBOX access 18-525 Integrated Circuit Design Project

15. Questions?