1. Flip-Flops Lecture L8.2 Section 7.1 – Book Sect. 8.1– Handout

2. Recall the !S-!R Latch !S !R Q !Q 0 0 1 1 0 1 !S !R Q !Q 1 1 0 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand 1 0 Set 1 0 Store 0 1 Reset 1 1 Disallowed Q 0 !Q 0

3. Edge-triggered D Flip-flop 0 1 1 1 0 1

4. 1 0 1 0 1 1 0 1

5. 1 0 1 0 1 0 1 1

6. 1 0 0 1 1 0 1 0

7. 1 1 0 0 1 0 0 1

8. 1 1 0 1 1 0 0 1

9. 0 1 1 1 0 1 0 1

10. D Flip-Flop CLK DQ !Q 0 0 1 1 1 0 X 0 Q 0 !Q 0 D CLK Q !Q D gets latched to Q on the rising edge of the clock. Positive edge triggered

11. Each Xilinx 95108 macrocell contains a D flip-flop Controlled inverter

12. Each Xilinx 95108 macrocell contains a D flip-flop Note asynchronous preset x Q.AP = x Note asynchronous reset Q.AR = y y Q.D = z z

13. Divide-by-2 Counter CLK Q0 Q0.D = !Q0 CLK DQ !Q Q0.D = !Q0 Q0 Q0.D !Q0

14. MODULE div2cnt TITLE 'Divide By 2 Counter' DECLARATIONS " INPUT PINS " PB PIN 70; " push-button switch (clock) " OUTPUT PINS " Q0 PIN 44 ISTYPE 'reg buffer'; " LED 16 div2cnt.abl CLK DQ !Q Q0.D = !Q0 Q0 Q0.D !Q0 Registered Buffer output

15. EQUATIONS Q0.C = PB; Q0.D = !Q0; test_vectors(PB -> Q0).C. -> 1;.C. -> 0;.C. -> 1;.C. -> 0;.C. -> 1;.C. -> 0; END div2cnt.abl (cont’d) CLK DQ !Q Q0.D = !Q0 Q0 Q0.D !Q0.C. means clock goes LO-HI-LO Power-on output Q0 = 0

16. A 1-Bit Register

17. A 4-Bit Register

18. J-K Flip-flops Q.D = J & !Q # !K & Q

19. J-K Flip-flops

20. T Flip-flops Q.D = T $ Q

21. T Flip-flops

22. MODULE Tdiv2cnt TITLE 'Divide By 2 Counter using T flip-flop' DECLARATIONS " INPUT PINS " PB PIN 70; " push-button switch (clock) " OUTPUT PINS " Q0 PIN 44 ISTYPE 'reg buffer'; " LED 16 EQUATIONS Q0.C = PB; Q0.T = 1; test_vectors(PB -> Q0).C. -> 1;.C. -> 0;.C. -> 1;.C. -> 0;.C. -> 1;.C. -> 0; END 1