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Spring 2007EE130 Lecture 39, Slide 1 Lecture #39 ANNOUNCEMENTS Late projects will be accepted –by 1:10PM Monday 4/30: 20 pt penalty –by 1:10PM Friday 5/4: 50 pt penalty Extra office hour with Frank today: 3-4PM in 382 Cory Quiz #6 Review Session this Friday? OUTLINE The MOSFET: Sub-threshold leakage current Gate-length scaling
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Spring 2007EE130 Lecture 39, Slide 2 Sub-Threshold Leakage Current We had previously assumed that there is no channel current when V GS < V T. This is incorrect. If S > F, there is some inversion charge at the surface, which gives rise to sub-threshold current flowing between the source and drain:
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Spring 2007EE130 Lecture 39, Slide 3 Sub-Threshold Slope S
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Spring 2007EE130 Lecture 39, Slide 4 How to minimize S?
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Spring 2007EE130 Lecture 39, Slide 5 MOSFET Scaling MOSFETs have scaled in size over time –1970’s: ~ 10 m –Today: ~50 nm Reasons: –Speed –Density
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Spring 2007EE130 Lecture 39, Slide 6 –I DS as L (decreased effective “R”) –Gate area as L (decreased load “C”) –Therefore, RC (implies faster switch) Benefit of Transistor Scaling
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Spring 2007EE130 Lecture 39, Slide 7 Circuit Example – CMOS Inverter
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Spring 2007EE130 Lecture 39, Slide 8 d is reduced by increasing I Dsat
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Spring 2007EE130 Lecture 39, Slide 9 Constant-Field Scaling Voltages and MOSFET dimensions are scaled by the same factor >1, so that the electric field remains unchanged
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Spring 2007EE130 Lecture 39, Slide 10 Constant-Field Scaling (cont.) Circuit speed improves by Power dissipation per function is reduced by 2
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Spring 2007EE130 Lecture 39, Slide 11 V T Design Trade-Off Low V T is desirable for high ON current: I Dsat (V DD - V T ) 1 < < 2 But high V T is needed for low OFF current: V T cannot be scaled aggressively! Low V T High V T I OFF,high VT I OFF,low VT V GS log I DS 0
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Spring 2007EE130 Lecture 39, Slide 12 Since V T cannot be scaled down aggressively, the power-supply voltage (V DD ) has not been scaled down in proportion to the MOSFET channel length
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Spring 2007EE130 Lecture 39, Slide 13 Generalized Scaling Electric field intensity increases by a factor >1 N body must be scaled up by to control short-channel effects Reliability and power density are issues
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Spring 2007EE130 Lecture 39, Slide 14 CMOS Scaling and the Power Crisis 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01 1E+02 1E+03 0.010.11 Gate Length (μm) Power (W/cm 2 ) Passive Power Density Active Power Density L g /V DD /V T trends increases in: Active Power Density ( V DD 2 ) ~1.3X/generation Passive Power Density ( V DD ) ~3X/generation Gate Leakage Power Density >4X/generation Source: B. Meyerson, IBM, Semico Conf., January 2004
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