1. Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 426 - VLSI System Design Lecture 4 - Advanced Verilog February 5, 2003

2. 2/5/03ECE 426 - Lecture 42 Announcements  Reading  Wolf: 8.1-8.3

3. 2/5/03ECE 426 - Lecture 43 Where we are...  Last Time:  Timing and Delay in Event-Driven Simulation  Verilog Delay Constructs  initial blocks  Tasks and Functions  Discuss Lab 1  Today  A Little More about Delay  System Tasks and Functions  A little more FSM coding  More Verilog features  Recent Developments in Verilog

4. 2/5/03ECE 426 - Lecture 44 Verilogger Demo - Delay module delay_test(in1, in2, out1, out2, out3, out4, out5); input in1, in2; output out1, out2, out3, out4, out5; reg out3, out4, out5; and #10 and1 (out1, in1, in2); assign #10 out2 = in1 & in2; always @(in1 or in2) #10 out3 = in1 & in2; always @(in1 or in2) out4 = #10 in1 & in2; always @(in1 or in2) out5 <= #10 in1 & in2; endmodule Structural Delay Blocking Delay (Behavioral) Interassignment Delay (Blocking Assignment) Interassignment Delay (Non-Blocking Assignment)

5. 2/5/03ECE 426 - Lecture 45 Guidelines for Using Delays  Use structural delays for accurate modeling of:  Primitive gate instantiation and #5 (c, b, a);  Continuous assignment assign #5 c = b & a;  Use blocking delays w/ blocking assignments to sequence testbench inputs (more about this later)  #5 a = 1;  #5 a = 0;  Avoid interassignment (RHS) delays  a = #5 b + c;  a <= #5 c + d;

6. 2/5/03ECE 426 - Lecture 46 Verilog Delays: More Information  Cliff Cummings, “Correct Models for Adding Delays to Verilog Models”, Proceedings HDLCON, 1999. Available at http://www.sunburst-design.com.

7. 2/5/03ECE 426 - Lecture 47 More about Verilog FSMs  Many ways to describe  Explicit Style 1 State register - clocked always block Next-state Logic - combinational always block Output logic - combinational always block (or assign)  Explicit Style 2 Next-state logic AND state register: clocked always block Output logic - combinational always block (or assign)  Implicit Style State sequence specified using multiple event control –@(posedge clk); –…–…

8. 2/5/03ECE 426 - Lecture 48 Coding FSMs - Explicit Style 1  Clocked always block - state register  Combinational always block -  next state logic  output logic

9. 2/5/03ECE 426 - Lecture 49 Coding FSMs - Explicit Style 2  Clocked always block  state register  next-state logic  Comb. always block  output logic

10. 2/5/03ECE 426 - Lecture 410 Coding FSMs - Explicit Style 3  Clocked always block  state register  next-state logic  output logic (REGISTERED) DQ DQ

11. 2/5/03ECE 426 - Lecture 411 Coding FSMs - Implicit Style  Use event control @posedge(clk) to mark state boundaries  State flow follows procedural flow  General form: always begin @(posedge clk);... statements... @(posedge clk);... statements... end

12. 2/5/03ECE 426 - Lecture 412 Implicit Style FSM  Key idea: if the FSM has no branching, describe in a always block with multiple @(posedge clk) module implicit (clk,... ); input clk; // other inputs, outputs always begin @ (posedge clk) // state S0 @ (posedge clk) // state S1 @ (posedge clk) // state S2 end endmodule S0 S1 S2

13. 2/5/03ECE 426 - Lecture 413 More about Implicit Style FSMs  Awkward when reset needed: module SUM3 (clk,... ); always begin: reset_label @ (posedge clk) if (reset) disable reset_label; else // function for state S0 @ (posedge clk) if (reset) disable reset_label; else // function for state S1... endmodule This is similar to “break” in Java/C/C++

14. 2/5/03ECE 426 - Lecture 414 Implicit Style FSM with Branching multiple @(posedge clk) module implicit (clk,... ); input clk; // other inputs, outputs always begin // state S0 @ (posedge clk) if (A) begin // state S1 @ (posedge clk) end else begin // state S2 @ (posedge clk) end endmodule S0 S1 S2

15. 2/5/03ECE 426 - Lecture 415 Implicit FSM Example: SAR Circuit module sar_implicit(clk, start, GT, E, RDY); input clk; input start; input GT; output [3:0] E; output RDY; reg [3:0] E; reg RDY; always begin... end endmodule See next Page

16. 2/5/03ECE 426 - Lecture 416 Implicit FSM Example: SAR Circuit always begin @(posedge clk); RDY <= 1'b1; if (start) begin @(posedge clk) RDY <= 1'b0; E <= 4'b1000; @(posedge clk); if (GT) E[3] <= 1'b0; E[2] <= 1'b1; @(posedge clk); if (GT) E[2] <= 1'b0; E[1] <= 1'b1; @(posedge clk); if (GT) E[1] <= 1'b0; E[0] <= 1'b1; @(posedge clk) if (GT) E[0] <= 1'b0; end

17. 2/5/03ECE 426 - Lecture 417 Implicit-Style FSM Tradeoffs  Advantages  Concise  High-level specification - lets synthesis worry about implementation details (like state codes)  Disadvantages  All outputs registered!  Difficult to debug synthesized hardware (no explicit state codes)

18. 2/5/03ECE 426 - Lecture 418 Verilog Stuff we Won’t Talk about Much  wait(condition)  suspends execution until condition true  Not used in synthesis  Procedural continuous assignment  assign / desassign as procedural statements  Not used in synthesis  User-Defined Primitives (UDPs)  Look-up table specification of primitive gates  Not used in synthesis  Programming Language Interface (PLI)  Allows simulation models to link to C programs  Not used in synthesis

19. 2/5/03ECE 426 - Lecture 419 Verilog - Recent Developments  Verilog 2001(IEEE Standard) - Adds several new features  Cleaner module specifications  Lots of “syntatic sugar” - features that make language “nicer” to use  Superlog / System Verilog  Meant to allow hardware/software codesign  Integrates many features of C: C primitive types Structures Enumerated Types

20. 2/5/03ECE 426 - Lecture 420 HDLs - What Else is Out There?  VHDL  More general; more verbose  Continued extension - VHDL 2001 is current standard  SystemC  C++ class library of synthesizeable constructs  Meant for large system hardware/software codesign  Reference: www.systemc.org

21. 2/5/03ECE 426 - Lecture 421 Coming Up  Verification and Testbenches  System Design Issues

22. 2/5/03ECE 426 - Lecture 422 A Snapshot of the HDL World  VHDL  Verilog / Verilog 2001  Superlog  SystemC

23. 2/5/03ECE 426 - Lecture 423 System Design Issues  ASM Diagrams  Synchronization & Metastability  Handshaking  Working with Multiple Clocks