1. Design and Implementation of VLSI Systems (EN0160)
Lecture 12: Logical Effort (2/2)
Prof. Sherief Reda
Division of Engineering, Brown University
Spring 2007
[sources: Weste/Addison Wesley – Rabaey/Pearson]
S. Reda EN160 SP’07

2. Summary of linear delay model
g: logical effort = ratio between input capacitance of the “template” gate size and the input capacitance of 1× inverter
h: electrical effort = ratio between load capacitance and the gate input capacitance (sometimes called fanout)
p: parasitic delay
represents delay of gate driving no load
set by internal parasitic capacitance
Unloaded delay =3RC
 12 ps in 180 nm process
40 ps in 0.6 mm process
S. Reda EN160 SP’07

3. Example: FO4 Inverter
Estimate the delay of a fanout-of-4 (FO4) inverter
Logical Effort: g =
Electrical Effort: h =
Parasitic Delay: p =
Stage Delay: d =
Absolute Delay: dabs =
S. Reda EN160 SP’07

4. Example: FO4 Inverter
Estimate the delay of a fanout-of-4 (FO4) inverter
Logical Effort: g = 1
Electrical Effort: h = 4
Parasitic Delay: p = 1
Stage Delay: d = 5
Absolute Delay: dabs = 12*5=60ps
The FO4 delay is about
200 ps in 0.6 mm process
60 ps in a 180 nm process
f/3 ns in an f mm process
S. Reda EN160 SP’07

5. Multistage logic networks
Logical effort generalizes to multistage networks
Path Logical Effort
Path Electrical Effort
Path Effort
Can we write F=GH?
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6. Can we write F = GH? No! Consider paths that branch: G = 1
F = g1g2h1h2 = 36 = 2GH
How to fix this problem?
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7. Branching effort Introduce branching effort
Accounts for branching between stages in path
Now we compute the path effort
F = GBH
Note:
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8. Logical Effort can help us answering two key questions
How large should be each stage in a multi-stage network to achieve the minimium delay?
What is the optimal number of stages to achieve the minimum delay
S. Reda EN160 SP’07

9. 1. What is the optimal size of each stage?
Delay is minimized when each stage bears the same effort
Gate 1 2
GND
Answer can be generalized. Thus, for N stages, minimum delay is achieved when each stage bears the same effort
S. Reda EN160 SP’07

10. Example: 3-stage path
Select gate sizes x and y for least delay from A to B
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11. Example: 3-stage path Logical Effort G = Electrical Effort H =
Branching Effort B =
Path Effort F =
Best Stage Effort
Parasitic Delay P =
Delay D =
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12. Example: 3-stage path Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27
Electrical Effort H = 45/8
Branching Effort B = 3 * 2 = 6
Path Effort F = GBH = 125
Best Stage Effort
Parasitic Delay P = = 7
Delay D = 3*5 + 7 = 22 = 4.4 FO4
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13. Example: 3-stage path Work backward for sizes y = 45 * (5/3) / 5 = 15
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14. 2. What is the optimal number of stages?
Consider adding inverters to end of path
How many give least delay?
Define best stage effort
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15. Optimal number of stages
has no closed-form solution
Neglecting parasitics (pinv = 0), we find r = (e)
For pinv = 1, solve numerically for r = 3.59
A path achieves least delay by using
stages
S. Reda EN160 SP’07