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 Thermal Variation: temperature has a direct impact on the delay of CMOS gates; thermal variation might cause timing failures  Process Variation: process.

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Presentation on theme: " Thermal Variation: temperature has a direct impact on the delay of CMOS gates; thermal variation might cause timing failures  Process Variation: process."— Presentation transcript:

1  Thermal Variation: temperature has a direct impact on the delay of CMOS gates; thermal variation might cause timing failures  Process Variation: process variation has increasing impact on circuit timing D ESIGN A UTOMATION FOR S ELF- A DJUSTING A RCHITECTURES Jieyi Long, Seda Ogrenci Memik Department of EECS, Northwestern University Introduction Self-Adjusting Architectures Global Feedback Loop Based Architectures Conclusions Future Work Challenges of VLSI CAD in the Nano Regime Existing Solutions  Following the convention design flow, circuits are designed conservatively, causing performance loss  Statistical analysis and optimization frameworks are not able to be tailored for each individual chip The Proposed Solution  Develop self-adjusting architectures which constantly detect the actual operating conditions and adapt to environmental changes instantaneously Global Feedback Loop Based Architectures Local Feedback Loop Based Architectures  “The Nervous System”: A set of sensors (thermal, delay, power sensors, …)  “The Muscles”: A set of adjustable elements  “The Brain”: One/Multiple central control unit(s) Sensors Adjustable Elements Control Stokes’s Theorem  A Set of Special Elements: Each monitors the changes in its neighboring region, and adjusts itself according to the changes  Global Correctness Guaranteed by Local Adjustments : Analogous to Stokes’s Theorem in calculus Automated placement of thermal sensors in Chip Multiprocessors Self-Adjusting Pipeline (SAP) Architecture Self-Adjusting Clock Tree Architecture (SACTA) Local Feedback Loop Based Architectures clk R1R1 R2R2 R3R3 More Vulnerable Less Vulnerable 1 Non-Uniform Placement 2 Uniform Placement Non-UniformNon-Uniform K-Means Clustering UniformUniform Interpolation  Non-uniform: not suitable for dense layout due to thermal coupling Given a 2-stage pipeline, determine the location of the delay sensors, and nominal delay of the adjustable skew buffers, such that the average performance of a batch is maximized  Improve the average performance of a batch of chips by 9.5%  Uniform placement: not rely on the given thermal profiles Observations  Interpolation method covers 98.7% of thermal emergencies with only 16 sensors per core Problem Definition Observations Given a fixed number of thermal sensors, determine the locations of the sensors such that the error in temperature measurement of the hottest spot is minimized Problem Solving  Stochastic Mixed-Integer Programming  Simulated Annealing θ/ºCθ/ºC x CLK R1R1 R2R2 R3R3 Given a one-dimensional pipeline, determine the base delay of the fixed and self- adjustable skew buffers, such that the timing is guaranteed across the target temperature range  SACTA is able to enhance the timing violation-free temperature range by 15°C on average Problem Definition Observations Problem Solving  Linear Programming  Generalized Min-Cost Flow f1f1 fifi f i+1 fnfn CLK Δθ s i - k i Δθ RiRi R i+1 RnRn R1R1  Novo thermal sensing architectures and sensor designs  Local feedback loop based architecture for general circuits  Self-adjustable active cooling systems  …  Novo thermal sensing architectures and sensor designs  Local feedback loop based architecture for general circuits  Self-adjustable active cooling systems  …


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