1. Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer / Wire Sizing Christoph Albrecht Synopsys, Inc., Mountain View formerly Research Institute for Discrete Mathematics, Bonn, Germany Andrew B. Kahng, Ion M ă ndoiu UC San Diego, La Jolla Alexander Zelikovsky Georgia State University, Atlanta ASPDAC 2002, Bangalore

2. Outline Previous Work Buffer Block-/ Site-Methodologies Floorplan Evaluation Problem Key Ingredient: Gadgets Multicommodity Flow Approximation Algorithm / Randomized Rounding Experimental Results

3. Previous Work Floorplan Chen et al. – BBL [VLSI’83], Dai et al. [TCAD’87], Cong [TCAD’91] Buffer Block Methodology Cong et al. [ICCAD’99], Tang&Wong [ISPD’00] Buffer Site Methodolgy Alpert et al. [DAC’01] Multicommodity Flow Approximation Algorithm Garg and Konemann [FOCS’98] Fleischer [SIDMA’00] Application to Global Routing Albrecht [ISPD’00 + TCAD’01] Application to Buffer Block Methodology Dragan et al. [ICCAD’00 + ASPDAC’01 + WADS’01]

4. Buffer-Block Methodology Cong et al. [ICCAD’99], Tang&Wong [ISPD’00], Dragan et al. [ICCAD’00 + ASPDAC’01]: Buffers inserted in blocks located within available free space Simplifies design by isolating buffer insertion from circuit block implementations

5. Buffer-Site Methodology Alpert et al. [DAC’01] Block designers leave “holes” in circuit blocks to be used for buffer insertion Alleviates congestion problems of buffer blocks

6. Buffer-Site Methodology Alpert et al. [DAC’01] Block designers leave “holes” in circuit blocks to be used for buffer insertion Alleviates congestion problems of buffer blocks

7. Buffer-Site Methodology Alpert et al. [DAC’01] Block designers leave “holes” in circuit blocks to be used for buffer insertion Alleviates congestion problems of buffer blocks

8. Floorplan Evaluation Problem Tile graph G to model congestion: wire capacity w(u,v): number of free routing channels between tile u and v. buffer capacity b(v): possible number of buffers in tile v. Netlist (source and sink pins given as sets of tiles) Maximum wireload of buffers / sources U Given:

9. Floorplan Evaluation Problem Tile graph G to model congestion: wire capacity w(u,v): number of free routing channels between tile u and v. buffer capacity b(v): possible number of buffers in tile v. Netlist (source and sink pins given as sets of tiles) Maximum wireload of buffers / sources U Given: Find: Pin assignment and feasible buffered routing for nets, subject to buffer and wire congestion constraints and minimizing the total routing area,  (#buffers) +  (total wirelength), where ,   0 are given scaling constants

10. Key Ingredient: Gadgets Tile graph G

11. Key Ingredient: Gadgets

12. Cap = b(u) Cap = w(u,v) Cap = b(v)

13. Key Ingredient: Gadgets Lemma: 1-to-1 correspondence between feasible buffered paths for net N in G and s – t paths in H. iii Cap = b(u) Cap = w(u,v) Cap = b(v)

14. Integer Program  px x GEvuvuwxEp GVvvbxEp xEpEp p p p p pvu p pv p p vu vu v v path feasible {0,1}, net,1 )(),( ),,(ν )( (μ | s.t. min 0, 0 ),(,             | || ||| |

15. Integer Program  px x GEvuvuwxEp GVvvbxEp xEpEp p p p p pvu p pv p p vu vu v v path feasible {0,1}, net,1 )(),( ),,(ν )( (μ | s.t. min 0, 0 ),(,             | || ||| | x p 0 Linear Relaxation 

16. Dual Linear Program GEvu vuw vby l v v i i )(),( ),(ν )(μ s.t. max 0 0      z u,v   D u 1  GVv)(  y v z u,v 0  0  l i   Ep Ep vu vu v v,,      || | | y v u   u    ppath

17. Solution Linear Relaxation = Multicommodity flow with set constraints Garg and Konemann [FOCS’98] Fleischer [SIDMA’00 ] Randomized Rounding Raghavan & Thomson [COMB’87]

18. x p =0, y v =  /  0 b(v), z e =  / 0 w(e), u=  /D, p i =  While  v b(v)y v +  e w(e)z e + Du < 1 For i = 1,…, #nets do If p i =  or weight(p i ) > (1+  ) l i Find path p i with min weight l i among s i -t i paths End If x p i = x p i + 1 For every v  V(G) and e  E(G): y v = y v ( 1 +  |p i  E v | /  0 b(v) ) z e = z e ( 1 +  |p i  E e | / 0 w(e) ) u = u( 1 +  (   v |p i  E v | +   e |p i  E e |) / D ) End For End While Output x scaled by the number of ‘While’ iterations Approximation Algorithm

19. Extensions Sink delay upper bounds (Elmore-Delay) Buffer-wire sizing and layer assignment Multi-pin nets

20. TestcaseAlgoWirelen.%LB Gap#Buffers%LB GapW_congestB_congestCPU ami49 RABID759211.87133921.510.930.36167 324 nets a9c3 RABID307235.64422511.950.600.44502 1526 nets playout RABID276016.38384015.040.450.64813 1663 nets xc5 RABID270608.35441023.250.840.81694 2149 nets Experimental Results

21. TestcaseAlgoWirelen.%LB Gap#Buffers%LB GapW_congestB_congestCPU ami49 RABID759211.87133921.510.930.36167 324 nets MCF67920.0711352.991.000.47314 a9c3 RABID307235.64422511.950.600.44502 1526 nets MCF290820.0038010.720.630.311082 playout RABID276016.38384015.040.450.64813 1663 nets MCF259460.0034282.700.510.321393 xc5 RABID270608.35441023.250.840.81694 2149 nets MCF251550.7338417.350.960.601641 Experimental Results

22. TestcaseAlgoWirelen.%LB Gap#Buffers%LB GapW_congestB_congestCPU ami49 RABID759211.87133921.510.930.36167 324 nets MCF67920.0711352.991.000.47314 MCF+PA60410.019914.871.000.50304 a9c3 RABID307235.64422511.950.600.44502 1526 nets MCF290820.0038010.720.630.311082 MCF+PA260570.0033760.750.580.301079 playout RABID276016.38384015.040.450.64813 1663 nets MCF259460.0034282.700.510.321393 MCF+PA231380.0030044.120.400.321386 xc5 RABID270608.35441023.250.840.81694 2149 nets MCF251550.7338417.350.960.601641 MCF+PA222650.0533404.870.980.501644 Experimental Results

23. Conclusions First coherent approach to floorplan definition, timing and congestion-driven buffered global route planning, wire/buffer sizing, layer assignment and pin assignment. Provably good results by multicommodity flow approximation algorithms and randomized rounding.