1. Group M3 Nick Marwaha Craig LeVan Jacob Thomas Darren Shultz Project Manager: Zachary Menegakis February 21, 2005 MILESTONE 5 Component Layout DSP 'Swiss Army Knife' Overall Project Objective: General Purpose Digital Signal Processing Chip

2. STATUS Design Proposal (Done) Architecture (Done) Size Estimates/Floorplan/Verilog (85% - comb/Wallace alterations) Gate Level Design (80% - comb/Wallace alterations) Component Layout (Done - However, continue to optimize) To Be Done Complete layout of functional blocks Wallace Tree Multiplier, etc. Schematic Make remaining adjustments for comb/Wallace Verification Test for adjusted blocks

3. DESIGN DECISIONS Comb Removed 8 floating point multipliers and a multiplexer (about ½ of the comb) Allows circuit to implement 3 of 4 functions that require the comb Transistor count significantly above 25K limit, however much of the comb is redundant Use of Wallace Tree Multiplier in place of matrix multiply Increases complexity of the design Compared between Traditional Wallace Tree and Wallace Tree with Booth Recoding Booth Recoding adds partial products in parallel and reduces space Chose to use Booth Recoding in order to optimize space

4. DESIGN DECISIONS Porosity of Basic Components Using only Metal 1 and Poly in order to ease global routing Imaginary Numbers Current circuit can only handle real #s since imaginary #s require significant additions to an already large and complex design Working on “what would be necessary” – possibly for soft IP

5. DESIGN DECISIONS cont Namea0a1a2b0b1b2c1N 1Differencer100100x 2Integrator1101000x 3Leaky Integrator1101000x 4Comb Filter10010018 5Bandpass Filter10100116 6CIC Interpolation Filter11010018 7dc Bias Removal1a.b0100x 8First-Order Equalizer1a.b0 100x 9Audio Comb10a.b1000x 10Moving Averager1101/N0018 11Second-Order IIR Filter1a.bbb 0x 12First-Order Delay Network1a.bbb 10x 13Second-Order Delay Network1a.bbb 10x 14Real Oscillator12cos(x)10 xx 15Second-Order Equalizer1a.b*cos(x)a.b1a.b*cos(x)1/a.b0x Now Only 1 Function Removed

6. DESIGN DECISIONS cont Comb Design Removed in order to prevent unmanageable design size

7. WALLACE TREE MULT. Traditional Wallace Tree Booth Recoding Wallace Tree

8. IMAGINARY NUMBERS Modifications for complex arithmetic: Complex addition 2 scalar adds Complex multiplication 4 scalar mults and 2 scalar adds 3 scalar mults and 4 scalar adds Complex division 8 scalar mults and 4 scalar adds

9. IMAGINARY NUMBERS Design and Transistor Count Changes with Imaginary Numbers: Comb: Div: 1  2 Mults 8  32 or 24 Adder 1  18 or 38 Biquad: 1 div  2 Mults 6  24 or 18 Adders 4  20 or 32 Comb: 32*1770 + 18*1839 = 89742 + 2*Divide + overhead OR…. 18*1770 + 38*1839 = 101,742 + 2*Divide + overhead Biquad: 24*1770 + 20*1839 = 79,260 + 2*Divide + overhead OR… 18*1770 + 32*1839 = 90,708 + 2*Divide + overhead TOTAL (ABSOLUTE MINIMUM): 179,002 + overhead Approximate count: 200,000 transistors *(much larger bit-width): min 2500 tran. each

10. FLOORPLAN UPDATE FP Multipliers FP Divider FP Divider FP Multipliers FP Adders FP Adders

11. SIZE ESTIMATES

12. COMPONENT LAYOUT NAND ANDOR

13. COMPONENT LAYOUT cont XORMUX-2x1

14. COMPONENT LAYOUT cont FULL ADDER

15. PROBLEMS & QUESTIONS Full Adder Currently using a 24 transistor design Pass gate design can reduce size, however problems with transistor sizing & buffering Problem: Timing issues with top level design. (recursive circuit).